Method and apparatus for synchronizing data and clock signals

An interface circuit adapted for use in a data transmission system having a data processor for generating data signals in an asynchronous serial manner, and having a data set having means for providing clock pulses and means for sending the data signals over a transmission line to a remote location in a synchronous manner under the control of clock pulses provided by said data set, comprising:

• receiving register means having a serial data input coupled to an output of said data processor means for receiving and storing the data signals from said processor, said receiving register means including status means for providing a status signal whenever said receiving register is storing a given number of said data signals;
• synchronizing means having first means coupled to a clock output of said data set, and being responsive to the clock pulses provided by said data set to provide first and second timing pulses related in frequency to the frequency of said clock pulses, and second means having an input connected to an output of said first means to receive said first timing pulses, and a further input coupled to said output of said computer for receiving said data signals, said second means being responsive to the data signals and said first timing pulses for providing clock signals for application to a clock input of said receiving register means to enable it to receive said data signals in synchronism with the clock pulses;
• buffer means having parallel data inputs connected to parallel data outputs of said receiving register means for temporarily receiving the synchronized data signals from said receiving register means;
• control logic means including transfer means having an input connected to an output of said status means to receive said status signal and a further input connected to a further output of said first means to receive said second timing pulses, said transfer means being responsive to said status signal and said second timing pulses to provide transfer signals for application to said receiving register means and said transmitting register means for transferring the synchronized data signals to said buffer means;
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• transmitting register means having parallel data inputs connected to parallel data outputs of said buffer means for receiving said synchronized data signals from said buffer means, means coupling a serial data output of said transmitting register means to a data input of said data set, and means connected between a clock output of said data set and a clock input of said transmitting register for extending the clock pulses to said transmitting register means to cause the synchronized data signals to be transferred in serial form to said data set for transmission thereby over said transmission line to said remote location.

An interface circuit adapted for use in a data transmission system having a data processor for generating asynchronous data signals and having a data transceiving means connected to a transmission line for sending the data signals over said transmission line to a remote location in a synchronous manner under the control of clock pulses provided by the data transceiving means comprising:

• a receiving register having an input shift register and a receiving buffer register, said input shift register having a serial input coupled to an output of said data processor means for receiving said data signals, and having parallel outputs connected to parallel inputs of said receiving buffer register, and status means for providing a status signal whenever said receiving buffer register is storing data signals;
• a transmitting register including a transmitting buffer register and an output shift register, said transmitting buffer register having parallel inputs connected to parallel outputs of said receiving buffer register, and having parallel outputs connected to parallel inputs of said output shift register, said output shift register having a serial output coupled to said data transceiving means;
• synchronizing means having first means coupled to said clock output of said data transceiving means, and being responsive to said clock pulses provided by said data transceiver means to provide first and second timing pulses related in frequency to the frequency of said clock pulses, and second means having an input connected to an output of said first means to receive said first timing pulses, and a further input coupled to said output of said data processor for receiving said data signals, said second means being responsive to said first timing pulses and to said data signals to provide said clock signals for application to a clock input of said input shift register to cause said data signals to be shifted into said input shift register whereby said data signals are synchronized with the clock pulses as the data signals are shifted into said input register;
• control logic having an input connected to an output of said status means to receive said status signal and a further input connected to a further output of said first means to receive said second timing pulses, said control logic being responsive to said status signal and said second timing pulses to provide transfer signals to said buffer storage registers for effecting the transfer of the data signals from said input shift register to said output shift register over the associated buffer storage registers;
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• means for extending said clock pulses to a clock input of said transmitting register to cause said data signals to be serially shifted out of said output shift register for transfer to said data transceiving means for transmission thereby over said transmission line to said remote location.