Self-aligned double implanted short channel V-groove MOS device

An integrated circuit containing a V-groove depletion type load transistor connected in series with a V-grooved enhancement type switching transistor, said integrated circuit comprising:

• a. a semiconductor body having a surface portion, a lightly doped p-type impurity therein,
• b. a first N-type region forming the source of said switching transistor selectively formed beneath and extending to said surface portion of said semiconductor body,
• c. a second N-type region forming the drain of said switching transistor and the source of said load transistor selectively located beneath and extending to said surface portion of said semiconductor body,
• d. a first V-groove adjacent said surface portion and extending into said semiconductor body, said first V-groove located between and intermediate but separated from said first region and said second region, said V-groove having first and second side surfaces and first and second end surfaces,
• e. a first, thin N-type, layer forming the source extension of said switching transistor extending from said source of said switching transistor, and terminating at said first side surface of said first V-groove,
• f. a second, thin N-type, layer forming the drain extension of said switching transistor extending from said drain of said switching transistor and terminating at said second side surface of said first V-groove,
• g. a third, p-type, layer forming a portion of the channel of said switching transistor, said third layer having a higher acceptor dopant concentration than said semiconductor body, underlying and adjacent to a portion of said first and said second layers,
• h. a third spaced N-type region forming the drain of said load transistor, said third spaced N-type region formed beneath and extending to said surface portion of said semiconductor body,
• i. a second V-groove adjacent said surface portion and extending into said semiconductor body, said second V-groove having first and second side surfaces and first and second end surfaces, said first side surface of said second V-groove exposing a portion of said source region of said load transistor and said second side surface of said second V-groove exposing a portion of said drain region of said load transistor,
• j. a fourth, p-type, layer having a higher acceptor dopant concentration than said semiconductor body, underlying and adjacent said surface portion of said semiconductor body, and surrounding said drain regions and source regions of both said switching and said load transistor,
• k. at least one insulating layer forming a gate dielectric covering the entire surfaces of said first and said second V-grooves,
• l. at least one conducting layer forming a gate electrode overlying the entire said first and said second V-groove atop said insulating layer,
• m. conductor means in electrical contact with said drain regions and said source regions of both said switching and said load transistors.

A self-aligned V-groove insulated gate field effect transistor comprising:

• a. a semiconductor body having a surface portion containing a low concentration of impurities of a first conductivity type,
• b. first and second spaced regions, forming the drain and source of said transistor, containing impurities of a second conductivity type located adjacent said surface portion of said semiconductor body,
• c. a V-groove adjacent said surface portion and extending into said semiconductor body intermediate said first and second spaced regions, said V-groove having first and second side surfaces and first and second end surfaces, said first and second spaced regions terminated at said first and said second side surfaces, respectively, of said V-groove,
• d. a third region forming a portion of the channel of said transistor, said third region having a higher concentration of impurities of said first conductivity type than that of said semiconductor body, said third region underlying and adjacent to portions of said first and second regions and terminated on all four surfaces of said V-groove,
• e. a fourth region, forming a channel stopper, having a higher concentration of impurity of said first conductivity type than that of said semiconductor body, said fourth region underlying said surface portion of said semiconductor body and surrounding said first spaced region, said second spaced region and said V-groove,
• f. at least one insulating layer forming the gate dielectric overlying the exposed surfaces of said V-groove,
• g. at least one conductor layer forming the gate electrode atop said gate dielectric,
• h. conductor means in electrical contact with said drain and said source regions.