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US 4,065,679 AGranted
Dynamic logic system
AssigneeTeletype Corporation
InventorRichard H. Heeren
Life of this patent
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Abstract
A dynamic logic system is disclosed in which a capacitor is charged by a clock signal through a gating device. The capacitor is either discharged or remains at its charged value in response to the impedance of a logic circuit. Two such systems are disclosed in which the output from the first logic system is applied as an input to the second logic system.
Claims2
In combination;
- a field effect transistor having a source, a drain and gate for providing an impedance condition between said source and said drain;
- a first controlled switch having a first control terminal and first and second controlled terminals, said switch being responsive to a signal applied to said control terminal for altering the impedance between said first and second controlled terminals;
- means for connecting said source and drain to said first and second controlled terminals providing first and second nodes, respectively;
- a second controlled switch having a second control terminal and third and fourth controlled terminals;
- means for connecting said second control terminal to said first node;
- a first capacitor having first and second electrodes;
- means for connecting said second node to said second electrode;
- means for providing a clock signal between said first electrode and said first node;
- means for applying said clock signal to said first control terminal;
- means for applying an information signal to said third controlled terminal;
- a second capacitor connected between said first electrode of said first capacitor and said fourth controlled terminal;
- and
- means for connecting said fourth controlled terminal to said gate of said field effect transistor.
10 more elements
Dependencies are inferred from the claim text.