Rate/time computer and control device

#1. Field of the Invention

#This invention relates to rate/time measuring devices and in particular to a control device for computing the activity period for each unit of a plurality of units and computing the charge therefor.

#2. Description of the Prior Art

#FIGS. 1a, 1b and 1c may be sequentially placed to provide the overall schematic block diagram of the rate/time computer and control device.

#The electronic circuit elements uitlized in a first preferred embodiment of the rate/time computer and control device will now be described with reference to FIGS. 1a, 1b, and 1c. The rate/time computer and control device includes 10 keyboard numerical switches 20 (first and second selecting means), the switches being numbered sequentially from zero to nine. The output of the keyboard numerical switches 20 is fed to a keyboard encoder 22 which decodes the information into BCD form which in turn is fed into a shift register 26. The keyboard encoder 22 also includes a keypunch output which is fed to a one shot 24. When one of the keyboard numerical switches 20 is depressed the one shot 24 is activated which eliminates any roll-over or any possibility of activating two of the keys at the same time. The one shot 24 also produces an output Q which clocks the shift register 26 to accept the input numbers sequentially, most significant digit first, with dead time therebetween. The output of the shift register 26 is fed to a latch 30 (first latch). The output of the latch 30 is then fed to a BCD to binary PROM 28 which converts the BCD output of the latch into a binary numerical form, which is then used to select the desired numerical address within each of the memories which will be subsequently discussed. The latch 30 is updated by the output of the keyboard encoder only when the system strobe is in the not position which will enable the gate 34 and the gate 35.

#The system strobe (S/ST) is an output signal at line 41 from a set-reset flip-flop 40. A not system strobe (which is abbreviated NOT/S/ST or S/ST), is an output of the set-reset flip-flop 40 which is complementary to the system strobe output 41. A READ switch 36 (check means) activates the set-reset flip-flop 40 which causes the system strobe 41 to go high (high as used hereinafter means a positive voltage or a binary 1 signal as compared to a ground, low voltage or binary 0 signal). The system strobe signal 41 is utilized at various points throughout the system for interlock protection for disabling certain functions at various points throughout the operating procedure. As an example, activating the READ switch 36 activates the set-reset flip-flop 40 causing the system strobe 41 to go high. This disables a gate 34 which in turn disables the latch 30. Other disabling functions will be explained subsequently.

#When the system strobe 41 goes high it also enables a gate 48 so that the keyboard numerical switches 20 may then be depressed to enter a rate representation. The selected rate representation numerals in BCD form are generated by the keyboard encoder 22 and pass through the shift register 26 and then into a rate latch 50 (second latch). The rate latch 50 is enabled by the gate 48 only when the system strobe 41 is high and the one shot 24 is high.