Error correcting circuit arrangement using cube circuits
AssigneeFujitsu Limited
InventorsTakashi Takezono, Hisashige Ando
Life of this patent
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Abstract
An error correcting circuit utilizing a cube circuit for correcting errors in data having n+1 bits in accordance with the syndromes S.sub.1 and S.sub.3 from a check matrix H. The circuit comprises a generator for generating syndromes S.sub.1 and S.sub.3, means for providing (S.sub.1 -a.sub.i) based on the modulo 2 calculation for the i.sub.th line vector ##EQU1## OF THE CHECK MATRIX H corresponding to each data bit d.sub.1, means for multiplying (S.sub.1 -a.sub.i) three times, check means for checking the coincidence between (S.sub.1 -a.sub.i) and (S.sub.3 -a.sub.i.sup.3), and an inverting means for inverting the d.sub.i bit when the coincidence is detected. In the present invention, by utilizing a cube circuit the check circuit can be simplified.
Claims9
Error correcting circuit utilizing a cube circuit for correcting errors in the data (d.sub.0 d.sub.1 d.sub.2 . . . d.sub.n) having n+1 bits in accordance with the syndromes S.sub.1 and S.sub.3, ##EQU11## which are obtainable from the calculation of a check matrix H for the BCH code ##EQU12## said error correcting circuit comprising:
- generator means for generating said syndromes S.sub.1 and S.sub.3 based on the check matrix H;
- means for providing a term (S.sub.1 - a.sub.i) based on the modulo 2 calculation to the i.sub.th line vector ##EQU13## of said check matrix H corresponding to each data bit d.sub.i ;
- means for multiplying said (S.sub.1 - a.sub.i) term by three times so as to cube said term;
- means for providing a term (S.sub.3 - a.sub.i.sup.3) based on the modulo 2 calculation to the i.sub.th line vector ##EQU14## of said check matrix H corresponding to each data bit d.sub.i ;
- check means for checking the accordance between the terms (S.sub.1 - a.sub.i).sup.3 -- and (S.sub.3 - a.sub.i.sup.3);
- and
- inverting means for inverting said d.sub.i bit when the accordance is detected.
Error correcting circuit utilizing a cube circuit for correcting errors in the data (d.sub.0 d.sub.1 d.sub.2 . . . d.sub.n) having n+1 bits in accordance with the syndrome S.sub.1 and S.sub.3, where ##EQU15## which are obtainable from calculation of the check matrix H for a BCH code, said error correcting circuit comprising:
- a read only memory for storing a conversion table for converting (S.sub.1 - a.sub.i) = (A.sub.0 A.sub.1 A.sub.2 A.sub.3 A.sub.4 A.sub.5) to (S.sub.1 - a.sub.i).sup.3 = (B.sub.0 B.sub.1 B.sub.2 B.sub.3 B.sub.4 B.sub.5),
- means responsive to a given value of (S.sub.1 - a.sub.i) for addressing said read only memory to cause readout of a corresponding value of (S.sub.1 - a.sub.i).sup.3,
- check means for checking the coincidence between the values of (S.sub.1 - a.sub.i).sup.3 and (S.sub.3 - a.sub.i.sup.3), and
- inverting means for inverting said d.sub.i bit when the coincidence is detected.
Error correcting circuit for correcting errors in the data (d.sub.0 d.sub.1 d.sub.2 . . . d.sub.n) having n+1 bits in accordance with the syndromes S.sub.1 and S.sub.3, ##EQU16## which are obtainable from the calculation of a check matrix H for the BCH code ##EQU17## said error correcting circuit comprising:
- means for generating said syndromes S.sub.1 and S.sub.3 from the check matrix H;
- means for providing a term (S.sub.1 - a.sub.i) based on the modulo 2 calculation to the i.sub.th line vector ##EQU18## of said check matrix H corresponding to each data bit d.sub.i ;
- means for cubing said (S.sub.1 - a.sub.i) term to provide (S.sub.1 - a.sub.i).sup.3 ;
- means for providing a term (S.sub.3 - a.sub.i.sup.3) based on the modulo 2 calculation to the i.sub.th line vector ##EQU19## of said check matrix H corresponding to each data bit d.sub.i ;
- means for detecting coincidence between (S.sub.1 - a.sub.i).sup.3 and (S.sub.3 - a.sub.i.sup.3);
- and
- means responsive to said coincidence detected by said detecting means for correcting said data bit d.sub.i.
Dependencies are inferred from the claim text.