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AssigneeKokusai Denshin Denwa Kabushiki Kaisha
InventorsHiroshi Sakaki, Sotokichi Shintani, Hidemi Kuroda
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In an automatic equalizer for regenerating a received digital signal, comprising a delay element train with a plurality of taps, a coefficient matrix circuit and a group of variable coefficient units, the structure of said coefficient matrix circuit being considerably simplified by introducing a simple adder and/or subtractor at the input and/or the output of said coefficient matrix circuit.
An automatic equalizer comprising a delay element train having a plurality of taps, one end of said train being connected to an input terminal, a coefficient matrix circuit having a symmetrical placement of elements which operate on each of the signals obtained from each tap of said delay element train through a plurality of adders and subtractors, multipliers providing a product of each tap output of a group of variable coefficient and an error signal between the output signal and the reference signal, a group of variable coefficient units controlled by said coefficient matrix circuit for providing an equalized output signal, a plurality of adders and subtractors provided at the input of said coefficient matrix circuit for adding pairs of signals to each other and subtracting pairs of signals from each other, said pairs of signals being obtained from outputs of taps of said delay element train.
An automatic equalizer comprising a delay element train having a plurality of taps, one end of said train being connected to an input terminal, a coefficient matrix circuit having a symmetrical placement of elements which operate on each of the signals obtained from each tap of said delay element train through a plurality of multipliers and adders and subtractors, said multipliers providing a product of each tap output of said train and an error signal between the output signal and the reference signal, a group of variable coefficient units controlled by said coefficient matrix circuit through a plurality of adders and subtractors, for providing an equalized output signal, a plurality of adders and subtractors provided at the input of said coefficient matrix circuit for adding pairs of signals to each other and subtracting pairs of signals from each other, said pairs of signals being obtained from outputs of taps situated symmetrically at said delay element train through said multipliers, a plurality of adders and subtractors provided at the output of said coefficient matrix circuit, said adders and subtractors comprising a transposed matrix of the matrix comprising the adders and subtractors at the input of said coefficient matrix circuit.
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
Arrangements for removing intersymbol interference: using neural networks
Time domain: neural networks
Digital communication
Term ended 20 Dec 1994 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
The present invention relates to an automatic equalizer utilized in a digital transmission circuit and, in particular, relates to the improvement of an automatic equalizer having a coefficient matrix.
A prior automatic equalizer having a coefficient matrix for instance, R. W. Chang: A New Equalizer Structure for Fast Start-Up Digital Communication, BSTJ Vol 50 1971 PP1969-1971 has a disadvantage in that the structure of the equalizer is complicated since the prior equalizer computes the whole coefficient matrix. This creates considerable redundancy.
It is an object, therefore, of the present invention to overcome the disadvantage and limitation of a prior automatic equalizer by providing a new and improved automatic equalizer.
The foregoing and other objects, features and attendant advantages of the invention will be appreciated as the same become better understood by means of the following description and the accompanying drawings wherein:
FIGS. 1 and 2 are block-diagrams of the prior automatic equalizers;
FIG. 3 is a block-diagram of the automatic equalizer according to the present invention;
First, a prior automatic equalizer is explained, with reference to FIGS. 1 and 2, for the sake of an easier understanding of the present invention.
FIG. 1 is a block-diagram of the prior automatic equalizer which has a coefficient matrix in the error signal unit and FIG. 2 is a block-diagram of the prior automatic equalizer which has the coefficient matrix in the signal path. For simplicity in the explanation, it is assumed in the following description that the equalizer has four delay taps. In FIGS. 1 and 2, the reference numeral 1 is a delay element train, 2 is a group of variable coefficient units, 3 is a group of multipliers, 4 is a comparator, 5 is a Q-coefficient matrix and 6 is a P-coefficient matrix. 100 is an input terminal, 200 is an output terminal, 300 is a terminal for receiving a correct signal and 400 is a terminal for providing an error signal. Although the operation of the equalizer shown in FIGS. 1 and 2 is well-known, the operation is briefly explained for the sake of the explanation of the present invention.
FIG. 1 is an automatic equalizer which has a coefficient matrix in an error signal path. The input signal from the input terminal 100 is sent to the output terminal 200 through a delay element train 1, each element of which delays the signal by the same time as the unit period of the input signal, and the group of variable coefficient units 2. The comparator 4 provides the difference between the output signal at the terminal 200 and the correct signal from the terminal 300, and the difference signal or the error signal appears at the terminal 400. The group of multipliers 3 provides the product of the error signal and each tap output of the delay element train 1. The output of the multipliers 3 is applied to the Q-coefficient matrix 5, in which a matrix computation is performed, and the output of the matrix 5 controls the group of variable coefficient units 2.