Custom watch

A method for keeping time in an integrated circuit having control means for selective generating an address and control signal, having a master oscillator for generation of a timekeeping signal coupled to said control means, and having output means for generating an output signal, comprising the steps of:

• decoding in response to at least in part to said timekeeping signal a first address and decoding a control signal;
• selectively accessing at least one cell within a RAM coupled to an address decoder means in response to said decoded first address and control signal;
• coupling the selected binary word stored in said accessed cell in said RAM to a memory means in response to a first control signal from said control means;
• and
• selectively coupling said selected binary word in said memory to at least one of said RAM, said output means, and a PLA.

An integrated circuit watch comprising:

• input means for generating at least one input signal;
• a master oscillator for generating a frequency standard signal;
• timing and control means coupled to said master oscillator and to said input means, said timing and control means generating at least one timing and control signal in response to said input signal and said frequency standard signal;
• address generation means coupled to said timing and control means, said address generation means generating an address signal in response to said timing and control signal;
• address decoder means coupled to said address generation means and to said timing and control means, said address decoder means decoding said address signal in response to said timing and control signal;
• a RAM coupled to said address decoder means and to said timing and control means, a selected binary word being read from said RAM in response to said timing and control signal;
• a PLA coupled to said address decoder means and to said timing and control means, said PLA generating an output binary word in response to said address signal and to said timing and control signal;
• memory means coupled to said RAM and PLA for selectively coupling said selected binary word from said RAM to said PLA;
• and
• output means coupled to said timing and control means, to said memory means, and to said address generation means, said memory means selectively coupling said selected binary word from said RAM to said output means, said output means selectively generating an output signal in response to said output binary word, in response to said selected binary word and in response to said timing and control signal.

An integrated circuit watch comprising:

• input means for generating at least one input signal;
• a master oscillator for generating a frequency standard signal;
• timing and control means coupled to said master oscillator and to said input means, said timing and control means for generating a plurality of timing signals and a plurality of control signals in response to said input signal and said frequency standard signal, said timing and control means including at least one PLA to selectively generate a plurality of control signals;
• address generation means coupled to said timing and control means, said address generation means for generating a plurality of address signals in response to said timing and control signal, said address generation means including a decoder - ROM circuit to selectively generate said plurality of address signals.
• address decoder means coupled to said address generation means and to said timing and control means, said address decoder means decoding said address signal in response to said timing and control signal;
• a RAM coupled to said address decoder means and to said timing and control means, a selected binary word being read from said RAM in response to said timing and control signal;
• a PLA coupled to said address decoder means and to said timing and control means, said PLA generating an output binary word in response to said address signal and to said timing and control signal;
• memory means coupled to said RAM and PLA for selectively coupling said selected binary word from said RAM to said PLA and from said PLA to said RAM, and
• output means coupled to said timing and control means, to said memory means, and to said address generation means, said memory means selectively coupling said selected binary word from said RAM to said output means and selectively coupling said output binary word from said PLA to said output means, said output means selectively generating a plurality of output signals in response to said output binary word, in response to said selected binary word and in response to said timing and control signal, said output means including a decoder - ROM circuit to selectively generate said plurality of address signals.