Automatic clock tuning and measuring system for LSI computers

An automatic clock tuning system including computing means of the type having a preloaded data memory providing control data to said tuning system for use in a data processing system of the type in which sequential fixed frequency clock pulses from a clock pulse source are utilized to time logic circuit operations comprising;

• a delay means for providing fixed frequency clock pulses in the data processing system with the delay determined by said control data from the data memory;
• a clock distribution means for distributing the delayed clock pulses received from said delay means in accordance with the clock path selection information contained in the control data obtained from the data memory;
• a reference generator connected to said source of fixed frequency clock pulses for introducing predetermined increments of delay to successive clock pulses and for selecting under control of said control data from said memory the one of said clock pulses having a delay substantially equivalent to the predetermined timing associated with the path to which said clock distribution means is set;
• an automatic time detecting means connected to said reference generator and to said clock distribution means for providing an output indicative of a comparison or non-comparison of the time of occurrence between one of the delayed clock pulses from said clock distribution means and said selected reference delayed clock pulse from said reference generator, the non-comparison condition output effecting an adjustment of the delay of said delay means through said computing means, said time detection repeating until a comparison of one of the delayed clock pulses and said reference delayed clock pulse is obtained thereby indicating that the clock pulses have the predetermined timing for the selected distribution path.