US 4,063,273 A · Fundamental logic circuit

Abstract

A logic circuit has the individual elements arranged in a semiconductor layer. The elements are in the form of field effect transistors having a multiple gate and bipolar transistors having a multiple emitter. The multiple gates of the field effect transistor represent the inputs of the fundamental logic circuit, and at least one emitter of the multiple emitters of the bipolar transistor represents the output of the fundamental logic circuit. The elements are arranged in the semiconductor layer in such a manner that a first supply voltage potential can be connected to the semiconductor layer. One configuration of the multiple gates of the field effect transistor identifies the circuit as a NAND circuit, while another configuration of the gates identifies the circuit as a NOR circuit. An additional element, a bipolar transistor, may be formed in the semiconductor layer and be connected to an emitter of the multiple emitter transistor to provide a power output stage in a Darlington configuration.

Claims13

Dependent claims

A logic circuit comprising:

a semiconductor layer having a terminal for receiving a supply potential;
and
a plurality of circuit elements carried by said semiconductor layer defining
a multiple gate field effect transistor the gates of which represent the logic inputs of said logic circuit, and
a multiple emitter bipolar transistor integrated with said field effect transistor, at least one of the emitters representing the output of said logic circuit.

2 more elements

A logic circuit comprising:

a doped semiconductor layer;
a terminal carried by said layer for receiving a first voltage supply potential;
first and second zones doped oppositely to said semiconductor layer and spaced apart therein to have a channel zone therebetween and define a source and drain, respectively, of a MOS field effect transistor;
an insulating layer carried by said semiconductor layer over the channel zone between said source and drain;
a plurality of gate electrodes for the MOS field effect transistor carried on said insulating layer insulated from each other and arranged in a pattern in which each covers a respective portion of the channel zone such that application of a voltage which is effective to form the channel requires application of the suitable voltage to at least one of said gate electrodes, said plurality of electrodes constituting the logic inputs of said logic circuit;
third and fourth zones doped oppositely to said second zone and spaced apart therein, said zone also constituting a base and said third and fourth zones consituting emitters and said semiconductor layer constituting the collector of a bipolar transistor, at least one of said emitters constituting an output for said logic circuit;
and
a load element in said semiconductor layer connected to said output and including a terminal for receiving a second voltage supply potential.

5 more elements

Dependencies are inferred from the claim text.

Fundamental logic circuit

Life of this patent

Fundamental logic circuit

Life of this patent

Abstract

Claims13