System for improving the resolution of alpha-numeric characters displayed on a cathode ray tube
OwnerOlaf H. Fernaldinventor
Life of this patent
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Abstract
A system is provided for displaying alpha-numerical data on a cathode ray tube. A flicker-free, high resolution display is achieved by a repeating raster field displaced slightly from one another. This is achieved in one approach by using a modified repeat field technique in a 10 .times. 14 display and an associated 10 .times. 14 memory for each letter. Another approach employs a 5 .times. 7 memory in conjunction with logic circuitry producing a resolution equivalent to a 10 .times. 14 display by means of fillets generated at selected portions of the characters. The shape of individual characters is improved by selectively removing fillets from square corners of the character by using the presence of a black or illuminated area to inhibit the use of a fillet.
Claims3
A system for displaying high resolution alpha-numeric characters each in a grid pattern of selectively illuminated spots of large and small elements, comprising
- a. a cathode ray tube,
- b. memory means including a fixed storage portion and a variable portion connected to said tube for storing encoded alpha-numeric characters in a grid pattern,
- c. input means connected to the variable portion of said memory means for feeding input information into said system,
- d. driving means connected to said memory means and said tube for generating a slightly displaced double raster grid matrix on said tube,
- e. timing means connected to said memory means and said driving means for cyclically repeating the output of said memory means in synchronism with said driving means,
- f. the fixed storage portion of said memory means storing encoded versions of said alpha-numeric characters in essentially a single grid element width format, and
- g. pattern control means connected to said memory and driving means to receive inputs therefrom for modifying the generated character of one raster with respect to the same character of the other raster;
- h. said pattern control means including logic circuitry connected between said memory means and said tube, said circuitry including gates receiving input signals from said memory with respect to large elements of each character being generated and adapted to produce a small element output signal to modify said character upon the occurrence of a predetermined combination of signals,
- i. said gates including an OR gate, and AND gate and an inverter receiving signals in one of two possible states with respect to an unknown portion of said character and providing an output of said tube,
- j. said gates and inverter connected in parallel with one of said gates being an output gate, said output gate connected to receive two input signals one of which corresponds to a grid area within which an unknown area fails, and the other of which is the output of said gates and inverter, said other gates and inverter connected to receive at least three other signals corresponding to other parts of said grid pattern,
- k. said circuitry expressing the algorithm A+ (B.multidot.C.multidot.D) and the logical equivalents thereof where A represents a signal corresponding to a grid area within an unknown area falls, B represents a signal corresponding to a horizontally adjacent area, C represents a signal corresponding to a vertically adjacent area, D represents a signal corresponding to a diagonally adjacent area and D represents the inversion of the signal D.
A circuit for storing information for use in a display system, comprising
- a. a read-only memory adapted to store digitally encoded alpha-numerical characters and symbols in a grid pattern of relatively large elements of low resolution,
- b. address input means connected to said memory to selectively read data stored therein,
- c. pattern control means connected to said memory and adapted to generate relatively small elements and additional data which combined with said memory data corresponds to digitally encoded alpha-numeric characters in high resolution for use in said display system,
- d. said pattern control means including an OR gate, an AND gate and an inverter receiving signals in one of two possible states with respect to an unknown portion of said character and providing an output to said display system,
- e. said gates and inverter connected in parallel with one of said gates being an output gate, said output gate connected to receive two input signals one of which corresponds to a grid area within an unknown area falls and the other of which is the output of the other of said gates and inverter, said other gates and inverter connected to receive at least three other signals corresponding to other parts of said grid pattern,
- f. said circuitry expressing the algorithm A + (B.multidot.C.multidot.D) and the logical equivalents thereof where A represents a signal corresponding to a grid area within which an unknown area falls, B represents a signal corresponding to a horizontally adjacent area, C represents a signal corresponding to a vertically adjacent area, D represents a signal corresponding to a diagonally adjacent area and D represents the inversion of the signal D.
Dependencies are inferred from the claim text.