Memory cell and array
AssigneeRCA Corporation
InventorRoger Green Stewart
Life of this patent
Estimating the term…
Abstract
An active storage or memory cell includes first and second high input impedance inverters cross coupled to form a flip-flop. The output impedance of the second inverter is significantly lower than the output impedance of the first inverter. Input signals are applied at, and information is read out from, a single input-output point common to the output of the second inverter and the input of the first inverter via a gating means connected between said input-output point and an input-output line which is turned on more slowly than it is turned off.
Claims12
The combination comprising:
- first and second inverters, each inverter having an input and an output, the inverters being characterized in that they both have a high input impedance and the output impedance of the second inverter being significantly less than the output impedance of the first inverter for the same turn on bias condition;
- a common input-output point;
- means cross-coupling the two inverters for forming a flip-flop including means connecting the output of the first inverter to the input of the second inverter, and negligible impedance means connecting the input of the first inverter and the output of the second inverter to said input-output point;
- and
- input means connected to said input-output point for selectively setting said flip-flop and for selectively sensing the state of said flip-flop.
The combination comprising a flip flop having an output point and a single gating transistor having its conduction path connected between said output point and a single sense line, and wherein for one value of stored data said gating transistor conducts in the follower mode whereby the value of the signal read out on said sense line is offset;
- a high input impedance inverter having an input and an output and first and second power terminals for the application therebetween of an operating potential;
- said input being connected to said sense line, and said output being connected to a data output line;
- and a feedback transistor of different conductivity type than said gating transistor having first and second electrodes defining the ends of its conduction path and a control electrode;
- said control electrode being connected to said data output line, one end of said conduction path being connected to said sense line and the other end of said conduction path being connected to that one of said first and second power terminals having a value to reduce said offset, whereby said feedback transistor, when turned on, reduces said offset.
Dependencies are inferred from the claim text.