MIS decoder providing non-floating outputs with short access time

A metal-insulator-semiconductor (MIS) decoder comprising:

• first MIS means coupled to an operating voltage and being turned on by a first pulse and precharging a first capacitor with current flowing therethrough;
• second MIS means coupled to a reference potential for providing a discharge path for the precharge of said capacitor by a second pulse in a non-selection mode;
• third MIS means having a source, a drain and a gate, said gate and drain being applied with the output of said capacitor and a third pulse respectively, and said source providing an output of the decoder in selection and non-selection modes, said third pulse being applied simultaneously with the application of said second pulse;
• fourth MIS means connected between the source of said third MIS means and the reference potential and having a gate applied with a voltage signal to hold the source of said third MIS means at the reference potential;
• and
• means, responsive to said first pulse and said second pulse, for providing a pulse signal having a pulse width equal to that of the first pulse plus a discharge time constant determined by the maximum on-resistance of said second MIS means completing the discharge path and the capacitance of said first capacitor upon application of said first pulse, and said pulse signal being applied to the gate of said fourth MIS means as said voltage signal.

An MIS decode circuit of the dynamic drive type including at least first and second decoders, each decoder comprising:

• a first MISFET turned on by a first pulse and precharging a parasitic capacitor by current flowing therethrough;
• an MIS gate circuit rendered inoperative in a selection mode and operative by a second pulse in a non-selection mode to produce a discharge path for the precharge of said parasitic capacitor;
• a second MISFET having a drain coupled to a third pulse, a gate connected to an output terminal of said parasitic capacitor, and a source from which the output of the decoder is derived in selection and non-selection modes, said third pulse being applied synchronously with said second pulse;
• a third MISFET series-connected between the source of said second MISFET and ground and having a gate connected to receive a control voltage for grounding the source of said second MISFET by the applied control voltage;
• and
• the output terminals of the parasitic capacitors of said first and second decoders being cross-coupled to the gates of their third MISFETs, thereby applying the terminal voltage of the parasitic capacitor of one of said first and second decoders as the control voltage for the other of said first and second decoders.

A MIS decoder circuit arrangement utilizing the charging and discharging of a capacitor comprising:

• a charging circuit for charging said capacitor;
• an output circuit made up of series connected first and second MISFETs having their drain-to-source paths connected in series between an enable signal input terminal and a reference potential terminal, the output of said decoder circuit arrangement being derived from the interconnection point of said first and second MISFETs, the gate of said first MISFET being connected to said capacitor, and the gate of said second MISFET being coupled to receive a control signal;
• a discharging circuit connected in parallel with said capacitor and being activated by a discharge signal so as to discharge said capacitor;
• and
• means, coupled to the gate of said second MISFET, for supplying thereto a control signal which causes said second MISFET to conduct, said control signal being such that said second MISFET is rendered conductive for a period of time equal to the duration of said enable signal plus a prescribed time constant corresponding to the product of the maximum on-resistance of said discharging circuit and the capacitance of said capacitor, whereby the voltage at the output of said decoder circuit arrangement is prevented from floating.