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AssigneeInternational Business Machines Corporation
InventorsEdward Baxter Eichelberger, Eugene Igor Muehldorf, Ronald Gene Walther, Thomas Walter Williams
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Propagation delay testing is performed on a generalized and modular logic system that contains embedded arrays and can be used as arithmetic/logical/control unit in a digital computer or data processing system. Each such unit can be composed of combinatorial logic and storage circuitry. The storage circuitry may be of two types, randomly arranged latches, or arrays of storage cells. In the organization presented here the latches are arranged such that they have the capability of performing scan-in/scan-out operations independently of system control. Using this scan capability, the method of the invention provides for the state of the storage latches to be preconditioned and independent of prior circuit history. Selected propagation paths are sensitized by patterns from an automated test generator or designer supplied patterns. By alternating selected inputs and by applying proper timing control, propagation delay indications through the selected paths are obtained to determine delay behavior of the logic system.
A method of propagation delay testing a single-sided delay dependent level sensitive embedded array logic unit having primary inputs and primary outputs and formed of interconnected combinational network circuit means, array circuit means and sets of sequential circuit means having access for scanning independent of said primary inputs and outputs, said method including the steps of:
A method of propagation delay testing a single-sided delay dependent level sensitive embedded array logic unit, said logic unit comprising:
A method of propagation delay testing a single-sided delay dependent level sensitive embedded array logic unit, said logic unit comprising:
A method of propagation delay testing a single-sided delay dependent level sensitive embedded array logic unit, said logic unit comprising:
A method of propagation delay testing a single-sided delay dependent level sensitive embedded array logic unit, at least first and second system clocks coupled to said unit,
A method of propagation delay testing a single-sided delay dependent level sensitive embeded array logic unit, at least first and second system clocks coupled to said unit, said unit having primary inputs and primary outputs and formed of combinational network circuit means, array circuit means and at least one shift register having shift register input, output and control means independent of said primary inputs and outputs, said method employing test apparatus having storage elements coupled to at least certain ones of said primary inputs and auxiliary latch circuit means coupled to at least certain ones of said primary outputs and said shift register, said method including the following steps:
Dependencies are inferred from the claim text.