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US 4,063,078 AGranted
Clock generation network for level sensitive logic system
AssigneeInternational Business Machines Corporation
InventorsSumit Das Gupta, Edward Baxter Eichelberger
Life of this patent
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Abstract
Disclosed is an improved clock generation network. The improved clock generation network is particularly adapted to, and has particular utility when employed in a Level Sensitive Logic System generally of the type disclosed in U.S. Pat. No. 3,783,254, of common assignee. The disclosed clock generation network also has particular utility in a Level Sensitive Embedded Array Logic System of the type disclosed in U.S. patent application Ser. No. 701,052, filed June 30, 1976, by Messrs. E. B. Eichelberger, E. I. Muehldorf, R. G. Walther and T. W. Williams and of common assignee.
Claims21
A semiconductor chip containing integrated circuitry for use in a digital computer of the like, comprising:
- a plurality of networks at least one of which is a combinational logic network, at least one of said networks being responsive to a set of input signals with each network providing at least a first set of signals;
- a clock generation system for generating a plurality of clock signal trains wherein the signals of each of said plurality of clock signal trains is non-overlapping in time duration with the signals of each other ones of said plurality of clock signal trains;
- plural sequential circuit means arranged in groups coupled to respective ones of said plurality of networks for receiving respective first sets of signals from said network under control of predetermined ones of said non-overlapping clock signal trains to store indications of the signals from its associated network and to provide a set of outputs for said indications;
- means coupling said output indications from the respective groups of plural sequential circuit means as sets of inputs to all networks except a network coupled to a sequential circuit means controlled by the clock signal train exercising control in providing the set of output indications.
- means for accepting the sets of output indications to provide an output response from said chip;
- said integrated circuitry on said semiconductor chip being further characterized in that said clock generation system wholly contained on and within said semiconductor chip comprises:
- a chip input terminal for receiving a periodic input;
- a plurality of interconnected logical circuit means connected to said input terminal;
- each of said plurality of logical circuit means providing a discrete one of said plurality of non-overlapping clock signal trains.
6 more elements
A functional logic unit for performing at least one predetermined logical function wherein the circuitry is organized and arranged to facilitate testing said unit, said unit comprising:
- a plurality of networks at least one of which is a combinational logic network, at least one of said networks being responsive to a set of input signals with each network providing at least a first set of signals;
- a clock generation system for generating a plurality of clock signal trains wherein the signals of each of said plurality of clock signal trains is non-overlapping in time duration with the signals of each other ones of said plurality of clock signal trains;
- plural sequential circuit means arranged in groups coupled to respective ones of said plurality of networks for receiving respective first sets of signals from said network under control of predetermined ones of said non-overlapping clock signal trains to store indications of the signals from its associated network and to provide a set of outputs for said indications;
- means coupling said output indications from the respective groups of plural sequential circuit means as sets of inputs to all networks except a network coupled to a sequential circuit means controlled by the clock signal train exercising control in providing the set of output indications;
- means for accepting the sets of output indications to provide an output response from said unit;
- said functional unit being further characterized in that said clock generation system includes:
- at least one unit input terminal for receiving a periodic input;
- at least first and second interconnected logical circuit means connected to said input terminal;
- each of said logical circuit means providing a discrete one of said plurality of non-overlapping clock signal trains, each of said plurality of logical circuit means being level sensitive and single sided delay dependent.
6 more elements
A clock generation network for providing first and second pulse trains, where each said pulse in said first pulse train is precisely time displaced from each said corresponding pulse in said second pulse train, said clock generation network comprising:
- an input terminal for receiving a periodic input;
- first and second interconnected logical circuit means connected to said input terminal;
- said first logical circuit means comprised of inverter circuit means and AND circuit means having an output for electrically manifesting said first pulse train;
- said second logical circuit means comprised of inverter circuit means and AND circuit means having an output for electrically manifesting said second pulse train.
1 more element
A level sensitive logic system for use in a digital computer of the like, comprising:
- a plurality of networks at least one of which is a combinational logic network, at least one of said networks being responsive to a set of input signals with each network providing at least a first set of signals;
- a clock generation system for generating a plurality of clock signal trains wherein the signals of each of said plurality of clock signal trains is non-overlapping in time duration with the signals of each other ones of said plurality of clock signal trains;
- plural sequential circuit means arranged in groups coupled to respective ones of said plurality of networks for receiving respective first sets of signals from said network under control of predetermined ones of said non-overlapping clock signal trains to store indications of the signals from its associated network and to provide a set of outputs for said indications;
- means coupling said output indications from the respective groups of plural sequential circuit means as sets of inputs to at least certain networks except a network coupled to a sequential circuit means controlled by the clock signal train exercising control in providing the set of output indications;
- means for accepting the sets of output indications to provide an output response from said system;
- said level sensitive logic system being further characterized by said clock generation system comprising:
- a chip input terminal for receiving a periodic input;
- a plurality of interconnected logical circuit means connected to said input terminal;
- each of said plurality of logical circuit means providing a discrete one of said plurality of non-overlapping clock signal trains.
6 more elements
Dependencies are inferred from the claim text.