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US 4,062,178 AGranted
Electronic timepiece
AssigneeKabushiki Kaisha Suwa Seikosha
InventorMotoyoshi Sakamoto
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AssigneeKabushiki Kaisha Suwa Seikosha
InventorMotoyoshi Sakamoto
Estimating the term…
A frequency regulating circuit for an electronic timepiece is provided. The electronic timepiece includes an oscillator circuit for producing a high frequency time standard signal and a divider circuit for producing a low frequency timekeeping signal in response to the high frequency time standard signal being applied thereto. The divider circuit includes a plurality of series-connected divider stages, the frequency of the low frequency timekeeping signal being determined by the number of divider stages. Each divider stage is adapted to produce an intermediate frequency signal representative of the count thereof. The frequency regulating circuit is particularly characterized by a first logic circuit adapted to receive certain of said intermediate frequency signals produced by the divider stages and in response to a coincident binary state of the intermediate frequency signals applied thereto, apply a control signal to each of the divider stages to adjust the count of each of the divider stages to the same binary state. A gating circuit is coupled intermediate each of the divider stages and the logic circuit and is adapted to select the manner in which certain of the intermediate frequency signals are applied to the logic gate and thereby regulate the frequency of the low frequency timekeeping signal.
In an electronic timepiece including oscillator means for producing a high frequency time standard signal, divider means for producing an unregulated timekeeping signal in response to said high frequency time standard signal, said divider means including n series-connected divider stages, the frequency of said unregulated timekeeping signal being determined by the number of n series-connected divider stages, each of said n divider stages being adapted to produce an intermediate frequency signal representative of the count thereof, the improvement comprising, a first logic gate means for receiving at least one of said intermediate frequency signals and inverted intermediate frequency signals from each of said n series-connected divider stages, and in response to said of said intermediate frequency signals and said inverted intermediate frequency signals applied thereto having a coincident binary level, being adapted to apply a control signal to each of said divider stages to thereby adjust the count of each of said divider stages to the same binary level, and n second logic gate means respectively coupled intermediate said n series-connected divider stages and said first logic gate means, each of said second logic gate means being adapted to receive and select an intermediate frequency signal and applya predetermined number of said intermediate frequency signals produced by k series-connected divider stages, where k = 0, 1, 2 . . . , n-1, to said first logic gate means, said second logic gate means being further adapted to invert and apply said intermediate frequency signals produced by said k + 1 through n divider stages to said first logic gate means, and n third logic gate selecting means coupled respectively to each of said n second logic gate means for selectively disposing a first plurality of k second logic gate means associated with k series-connected divider stages, where k = 1, 2, . . . , n-1, to directly apply said intermediate frequency signal to said first logic gate, said remaining n third logic gate selecting means being adapted to dispose each of said second logic gate means coupled to said k + 1 through n series-connected divider stages to invert said intermediate frequency signals applied thereto and, in turn, apply same to said first logic gate means, said intermediate frequency signals produced by said divider stages being applied as a first input to said respect second logic gate means and wherein a second input of each of said 1 through n - 1 second logic gate means is the respective outputs of said 2 through n third logic gates, the first input of said nth third logic gate means being referenced to a high binary level, and wherein the second input of each of said n third logic gate means includes a select terminal, said k select terminal being adapted to reference each of said inputs to k third logic gate means, and in turn, k second logic gate means to an open state to thereby apply each of said intermediate frequency signals produced by k series-connected divider stages to said first logic gate means, said remaining k + 1 through n third logic gate select means being adapted to dispose each of said second logic gate means to which same are coupled to invert said intermediate frequency signals applied thereto.
In an electronic timepiece including oscillator means for producing a high frequency time standard signal, divider means for producing an unregulated timekeeping signal in response to said high frequency time standard signal, said divider means including n series-connected divider stages, the frequency of said unregulated timekeeping signal being determined by the number of n series-connected divider stages, being adapted to produce an intermediate frequency signal representative of a count thereof, the improvement comprising, a first logic gate means for receiving at least one of said intermediate frequency signals produced by said n series-connected divider stages, and in response to each of said intermediate frequency signals applied thereto having a coincident binary level, being adapted to apply a control signal to each of said divider stages to thereby adjust the count of each of said divider stages to the same binary level, n second logic gate means respectively coupled intermediate each of said n series-connected divider stages and first logic gate means, each second logic gate means being adapted to receive said intermediate frequency signal produced by said divider stage associated therewith, each said second logic gate means being disposed in one of an open state and a closed state for preventing a predetermined number of intermediate frequency signals produced by k series-connected divider stages, where k = 0, 1, 2 . . . , n - 1, from being applied to said logic gate means, said remaining second logic gate means being disposed to apply the intermediate frequency signals produced by k + 1 through n divider stages to said first logic gate, to thereby produce a regulated timekeeping signal, and including n third logic gate selecting means respectively coupled to each of said n second logic gate means for selectively disposing a first plurality of k second logic gate means associated with said k series-connected divider stages, where k = 1, 2, . . . , n - 1, in a first state to prevent said intermediate frequency signals from being applied to said first logic gate, said remaining n third logic gate selecting circuit means being adapted to dispose the remaining second logic gate means coupled to said k + 1 through n series-connected divider stages in a second state to thereby apply said intermediate frequency signals received thereby to said first logic gate means so that said intermediate frequency signals produced by said divider stages are applied as a first input to said respective second logic gate means and wherein a second input of each of said 1 through n - 1 second logic gate means is the respective outputs of said 2 through n third logic gate means, the first input of said nth third logic gate means being referenced to a high binary level, and wherein the second input of each of said n third logic gate means includes a select terminal, said select terminals being adapted to reference each of the inputs of k third logic gate means, and in turn, k second logic gate means to a closed state to thereby prevent each of said k intermediate frequency signals from being applied to said first logic gate means, said remaining k + 1 through n third logic gate means being adapted to disposed each of said second logic gate means to an open condition to apply said intermediate frequency signals received thereby to said first logic gate means.
Dependencies are inferred from the claim text.