US 4,062,042 AGranted

D.C. controlled attenuator

AssigneeElectrohome Limited

InventorArthur Richard Ott

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Abstract

A D.C. controlled attenuator which is particularly useful as a D.C. controlled video attenuation circuit providing three tracking channels that can be used as a tracking contrast control in an RGB monitor includes an integrated circuit having at least six MOS field effect transistors on a common substrate, the transistors being of N-channel and P-channel type and being arranged in the three groups of two each connected in complementary symmetry. In each group the gate electrodes of the N-channel and P-channel transistors are connected together, their drain electrodes are connected together and a source of D.C. potential is connected between their source electrodes in parallel. A variable resistor is connected between the gate electrodes of the transistors of a group and the drain electrodes of those transistors providing a feed forward signal path that also preferably includes a variable inductance coil. Input signals are supplied to the gate electrodes of the transistors, and the magnitude of the D.C. potential of the source of D.C. potential can be varied. By adjusting the value of the resistor in the feed forward signal path, cancellation of the signal at the drain junction of the COS MOS amplifier can be achieved at maximum gain of the amplifier, so that when the gain of the amplifier is reduced, less attenuation results.

Claims9

Dependent claims

A D.C. controlled attenuator comprising an integrated circuit including at least four MOS field effect transistors on a common substrate, said transistors including at least first and second n-channel and at least first and second p-channels transistors each having drain, source and gate electrodes, said first n-channel and p-channel transistors being connected in complementary symmetry with said gate electrodes thereof being connected together, said drain electrodes thereof being connected together and a source of D.C. potential connected between said source electrodes thereof, said n-channel and p-channel transistors being connected in complementary symmetry with said gate electrodes thereof being connected together, said drain electrodes thereof being connected together, and said source of D.C. potential being connected between said source electrodes thereof, a first variable resistor connected between said gate electrodes of said first transistors and said drain electrodes of said first transistors providing a first feed signal path, a second variable resistor connected between said gate electrodes of said second transistors and said drain electrodes of said second transistors providing a second feed forward signal path, means for supplying a first input signal to said gate electrodes of said first transistors, means for supplying a second input signal to said gate electrodes of said second transistors, and means for varying the magnitude of the D.C. potential of said source of D.C. potential.

Dependencies are inferred from the claim text.