Semi-conductor integrated circuit
AssigneeKabushiki Kaisha Suwa Seikosha
InventorIzuhiko Nishimura
Life of this patent
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Abstract
An improved semi-conductor integrated circuit wherein the likelihood of permanent breakdown of reverse junctions in the integrated circuitry in response to unexpected high voltages applied thereto is substantially reduced. The semi-conductor integrated circuitry includes at least two field-effect transistors and defines a circuit having at least one output terminal. At least one of the field-effect transistors includes a drain output terminal, and a resistance for reducing the secondary breakdown at the drain output terminal of the reverse junction between the drain output terminal and the semi-conductor integrated circuit substrate, said resistance being disposed intermediate said drain output terminal and said circuit output terminal.
Claims9
A semi-conductor integrated circuit comprising in combination, a C-MOS circuit formed of at least a P-channel field-effect transistor and an N-channel field-effect transistor, said circuit having respective input and output terminals, said field-effect transistors having commonly coupled drain output terminals, resistance means for reducing the secondary breakdown of said field-effect transistors, said resistance means being coupled intermediate said commonly coupled drain output terminals and said circuit output terminal, power terminals, and a stopper region associated with said drain output terminal, said stopper regions being referenced to one of said power terminals, the distance between at least one of said drain output terminals and said associated stopper regions defining a junction region adapted to be subject to primary breakdown at a voltage lower than a predetermined voltage, said predetermined voltage being lower than the primary breakdown voltage of the remaining junction of said C-MOS circuit.
Dependencies are inferred from the claim text.