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US 4,062,036 AGranted
Junction field effect transistor of vertical type
AssigneeNippon Gakki Seizo Kabushiki Kaisha
InventorTakashi Yoshida
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Abstract
A junction field effect transistor of vertical type whose gate region is formed on the drain region so as to protrude into the source region side. This gate region is formed to have a sufficiently minute dimension by relying on either the selective etching method, the selective oxidizing method, or the selective chemical vapor deposition method, whereby the area of junction can be substantially reduced, resulting in a marked decrease in junction capacitance, and a high current capability can be obtained.
Claims8
A vertical-type junction field effect transistor comprising:
- a drain region provided on a highly doped semiconductor substrate having a certain conductivity type and made of a semiconductor body having a conductivity type the same as that of said substrate and having a low impurity concentration,
- a source region formed on one surface of said drain region and made with a semicondutor body having a conductivity type the same as that of said drain region and having throughout a substantially constant impurity concentration not lower than that of the drain region, and
- a gate region provided at the intersurface between said drain region and said source region and having a conductivity type opposite to the conductivity type of said drain region and source region,
- said gate region being formed on the surface of said drain region between said drain and said source regions and protruding only into said source region.
1 more element
Dependencies are inferred from the claim text.