Digital radar signal processor

#FIG. 1 is a block diagram representation of the major sub-units of the preferred embodiment of the invention.

#FIGS. 2a and 2b, when placed side by side, with FIG. 2a on the left, constitute a block diagram showing the preferred embodiment in more detail.

#FIG. 3 shows logic circuitry embodying the address input matrix included in FIG. 2a.

#Referring to FIG. 1, a functional block diagram of the invention is shown. A conventional radar antenna and multiplexer or rat-race switch 12 act to both receive and transmit radar signals. A transmitter 14 and receiver 16 are connected to the digital signal processor 18 of the present invention. A signal is sensed by the antenna unit 12 and fed to the receiver 16 on line 20. The received signal is then fed by line 22 to a digital matched-filter 24 where it is processed through and then fed on line 26 to an acquisition processor 28. A track processor 30 also receives input signals from the receiver 16 via two lines 22 and 32. The track processor 30 extracts error information from the signals on these two lines and uses such information to close the track loops. The track processor 30 also regenerates the code at the track point and feeds it to the receiver 16 on line 33. A track synchronizer 34 supplies signals so that the digital signal processor 18 can operate with the transmitter 14 and receiver 16. More specifically, the track synchronizer 34 produces: a digital matched filter code signal which is fed to the digital matched filter 24 on line 36; a reference signal fed to the track processor 30 on line 37; a transmitter code and gate signal which is fed to the transmitter 14 on line 38; and an angle reference code signal fed to the receiver 16 on line 39.

#The digital signal processor of FIG. 1 is shown in more detail in FIGS. 2a and 2b. Referring to FIG. 2a, the acquisition signal processor, 28 of FIG. 1, uses a double threshold detection process to detect the target within the range acquisition interval defined by the radar operating mode and the designated range position. The first threshold set, shown generally at 40, utilizes automatically adjustable constant false alarm threshold detection; the second threshold set uses a background averaging technique. The first threshold set 40 has a first threshold detector 42 which acts as the element under control and receives the video signal on line 26. A noise gate generator 46, a false alarm counter 48, an expected threshold count 49, an interval counter 51, a comparator 52 and a threshold register 54 act as a digital constant false alarm rate unit. In order to establish a threshold unit which updates itself, a closed loop is established comprising the elements: first threshold detector 42, false alarm counter 48, comparator 52, threshold register 54, and a Digital/Analog converter 56 which feeds back into the first threshold detector 42. Control and sample functions are provided by noise gate generator 46, expected threshold count 49, and interval counter 51. In operation, the loop establishes a threshold level as follows. An analog noise signal on line 26 from receiver 16 enters first threshold detector 42 which senses the amplitude of the noise signal to determine when it is above a level set by the detector 42. The signal in detector 42 is converted into pulses from the continuous analog form by clock 80 which permits the noise signal to be fed into first threshold detector 42 only when the clock generates pulses. The output from detector 42 thus takes the form of clocked noise pulses on line 45. The false alarm counter 48 counts the number of clocked noise pulses on line 45 which occur within a noise gate generated by the noise gate generator 46 during the radar dead time (determined via connection line 47 from receiver 16). This number of noise pulses is summed over a number of pulse repetition periods (during radar dead time) in the false alarm counter 48 and compared to an expected false alarm number which is fed from expected threshold count unit 49 at the end of a preset time determined by interval counter 51. If the output of the false alarm counter 48 exceeds or is less than the expected false alarm number, a signal is produced by the comparator 52 and the threshold register 54 is counted up or down accordingly. The output of the threshold register 54 is fed to a digital to analog converter 56 which produces the required analog feedback signal on line 44 to adjust the first threshold detector 42. In essence, the first threshold level is determined by counting the actual false alarms, i.e., the noise pulses which exceed the level during the aforementioned preset time, comparing the actual false alarms with the expected number of false alarms, and then adjusting the threshold level up if there are more actual false alarms than expected false alarms or down if there are more expected than actual false alarms.

#The output signal on line 45 from the threshold detector 42 is fed into live-time n-word buffer shift registers 58 and 60. A "one" is fed into the shift registers 58 and 60 if the acquisition video input, on line 26, is above the first threshold level (as set by the threshold detector 42) and a "zero" is clocked in if it is below such level. The routing of the live-time data into the n-word buffer shift registers 58 and 60 is controlled by signals on line 62 from a processor timing control 68.