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US 4,062,007 AGranted
Solid-state delay timed switching circuit
AssigneeP. R. Mallory & Co. Inc.
InventorCharles E. Scott
Life of this patent
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Abstract
A solid-state delay timed switching circuit includes a delay timing means for delaying the start of an operational sequence. A function timing means is provided for timing the operational sequence, an alarm timing means for timing an audible alarm at the completion of an operational sequence, a power switching means, a power supply and a power turn-off means to de-energize the power switching means.
Claims11
A solid-state delay timed switching circuit comprising, in combination:
- a. a power switching means,
- b. a power supply means responsive to said power switching means,
- c. a single delay timing means electrically coupled to said power supply means for providing a time delay before the start of an operational sequence of functions which includes a first bi-directional semiconductor switch,
- d. a function timing means responsive to said delay timing means for timing an operational sequence of functions for predetermined times,
- e. a power turn-off means directly responsive to said function timing means for de-energizing said power switching means at the conclusion of the timing cycle of said function timing means which includes a second bi-directional semiconductor switch, and
- f. an alarm timing means responsive to said power turn-off means providing an audible alarm at the conclusion of the timing cycle said function timing means for a predetermined time.
3 more elements
Dependencies are inferred from the claim text.