Dual range, torque rebalancing of inertial sensor

#1. Field of Invention

#This invention relates to torque rebalancing of inertial sensors, and more particularly to a dual range torque rebalance feedback loop control apparatus and output integrator for use with torque rebalanced inertial sensors.

#2. Description of the Prior Art

#FIG. 1 is a schematic block diagram of a system incorporating the preferred embodiment of the present invention;

#FIG. 2 is a simplified block diagram of a timing generator for use in the embodiment of FIG. 1;

#FIG. 3 is an illustration of the timing of circuit operation, on a common time base;

#Referring now to FIG. 1, a system incorporating an exemplary embodiment of the present invention employs a rate integrating gyro 10 as the inertial sensor. As shown in FIG. 1, the gyro is a single axis gyro of the strapped-down variety (ungimballed), having a secondary winding 12 disposed to sense a varying amount of a carrier signal applied to a primary winding 14 coupled thereto, in proportion to any angular rate with respect to the input axis of the gyro. The carrier signal in the primary 14 may be provided in any suitable fashion, such as on a line 16 from a 23 KHz carrier oscillator 18. The output of the secondary 12 on a line 20 is a carrier signal whose magnitude is a function of angular rate sensed by the gyro. This signal is applied along with the carrier signal on the line 16 to an analog to pulsewidth modulation converter circuit 22, which is described more fully hereinafter with respect to FIG. 4, and which receives a 1 KHz reset signal on a line 24 and a 32 KHz signal on a line 26 from a timing generator 28, which is described more fully with respect to FIGS. 2 and 3 hereinafter. The circuit 22, in response to these timing signals, provides a ramp voltage which advances from maximum negative at the start at each 1 KHz cycle to maximum positive at the end of each cycle, which is compared against the magnitude of a signal indicative of angular rate derived from the signal on the line 20, successful comparisons in the first half of the cycle indicating negative rates and in the second half of the cycle indicating positive rates, early in the first half cycle indicating high negative rates and later in the first half cycle indicating lower negative rates, early in the second half cycle indicating lower positive rates and later in the second half cycle indicating higher positive rates. When the comparison occurs, the circuit 22 shifts from generating a positive feedback signal on a line 30a (to torque-rebalance negative rates) to generating a negative feedback signal on a line 32a (to torque-rebalance positive rates) thereby to control the polarity of current applied by lines 34, 36 to a rebalance torque winding 38 in the gyro 10, under the control of a regulated current source and +/- selection bridge 40, which is described more fully hereinafter with respect to FIG. 7. When a successful comparison is made, the circuit 22 also switches from generating a count-down signal on a line 30b to generating a count-up signal on the line 32b so that it transfers from integrating potentially negative rates in an output counter and integrator 45 (described more fully hereinafter with respect to FIG. 6) to integrating positive rates therein. The circuit 22 also provides in response to a successful comparison a mode shift time signal on a line 46 for comparing the angular rate indicated by the time of the successful comparison with a high rate strobe signal on a line 48 and a not low rate strobe signal on a line 50 in a mode control circuit 52 which is described more fully with respect to FIG. 5 hereinafter. If the timing indicated by the signal on the line 46 indicates a need to shift from one mode to the other, then the mode control will alter its operation as between providing a low mode signal on a line 54 and a high mode signal on a line 56. These signals control the magnitude of the ramp voltage in the circuit 22, the frequency of a clock signal which advances the output counter 45 and the magnitude of the torque rebalancing current provided by the regulated current source 40, as described briefly hereinbefore and more fully hereinafter. The timing generator 28 also provides, to the mode control 52 and the output counter 46, additional clock signals on lines 50-61 as is described more fully hereinafter. The output counter and integrator 45 provides a digital signal indicating an integrated angle on a trunk of 12 lines 62.

#Referring now to FIG. 2, an exemplary circuit, which of course may take a large number of other suitable forms, is shown for generating various clock and control signals for the system of the present embodiment. Specifically, a 256 KHz square wave oscillator 64 provides the 256 KHz clock signal on the line 60, and is also applied to a divide-by-8 circuit 66 (which may comprise a simple, three-stage binary counter) to provide the 32 KHz signal on the line 26. This is in turn applied to a divide-by-32 circuit 68 (which may be a simple, five-stage binary counter) to provide the 1 KHz signal on the line 59. The two counters 66, 68 can as well be thought of as a single eight-stage binary counter, so that the outputs thereof can be decoded to provide signals at particular times. Stages of the counters 66, 68 are applied by trunks of lines 70, 72 to a 256-counter-decode circuit 74 which decodes the 254th count, as indicated by a signal on a line 76, and decodes the 256th count as indicated by a signal on a line 78. These are used to respectively set and reset a bistable device such as a flip-flop or latch 80 to generate the 1 KHz reset signal on the line 24 as shown in illustrations (a) and (b) of FIG. 3. The outputs of all the stages of the divide-by-32 counter 68 are also applied to a 32-counter-decode circuit 82 to generate signals on a plurality of lines 84-87 respectively indicating counts of 2, 15, 18 and 31. The counts of 31 and 2 on the lines 87 and 84 are applied to a bistable device 88 to generate the high rate strobe signal on the line 48 as shown in illustration (e) of FIG. 3; the counts of 18 and 15 on the lines 86 and 85 are used to set and reset, respectively the bistable device 90 for generating the not low rate strobe signal on the line 50 as is shown in illustration (f) of FIG. 3.

#The 1 KHz signal on the line 59 is applied to a divide-by-32 counter so as to generate the 31.2 Hz signal on the line 58, which is not shown in FIG. 3 since it has a period 32 times greater than the time base illustrated in FIG. 3. The 1 KHz signal on the line 59 is also applied to a divide-by-16 counter 94, the outputs of which on a trunk of lines 96 are applied to a 10 decode circuit 98 which provides the 100 Hz signal on the line 61 and resets the divide-by-16 counter every time a count of 10 is reached. This signal is also not shown in FIG. 3 since it has a period 10 times greater than the time base illustrated in FIG. 3.