Timing recovery for an automatically equalized data modem
AssigneeHycom Incorporated
InventorsDavid M. Motley, Naif D. Salman, King Y. Cheng
Life of this patent
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AssigneeHycom Incorporated
InventorsDavid M. Motley, Naif D. Salman, King Y. Cheng
Estimating the term…
In a receiver, an analog-to-digital converter is adapted to sample a distorted analog signal to provide a plurality of distorted digital symbols separated in time by a particular interval. In an equalizer, taps are provided with variable multiplying coefficients which sequentially multiply the distorted digital symbols to provide undistorted digital symbols. A timing control network is responsive to variation in one of the multiplying coefficients to control the timing of the converter and hence the duration of the particular interval.
An apparatus for removing at least some of the distortion from an analog signal, said apparatus comprising:
An apparatus for removing at least some of the distortion from an analog signal, said apparatus comprising:
An apparatus adapted to receive a distorted analog signal comprising:
An apparatus for removing at least some of the distortion from a modulated analog signal, said apparatus comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Detection of the synchronisation error by features other than the received signal transition: detection of error based on equalizer tap values
Digital communication
Term ended 6 Dec 1994 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
This invention relates generally to modems, and more specifically to a timing network responsive to equalization multiplying coefficients to recover and control the timing of an automatic digital modem.
2. Description of the Prior Art
These and other features and advantages of the present invention will be more apparent with a discussion of the preferred embodiments taken in conjunction with the associated drawings.
FIG. 1 is a block diagram of a data transmission system comprising a transmitter and a receiver including one embodiment of the timing correction apparatus of the present invention;
FIG. 2 is a block diagram of the transmitter shown in FIG. 1;
The present invention concerns digital modems which facilitate the transmission of digital data between at least a pair of data processing apparatus which are disposed to communicate with each other over a telephone line. A first such data processing apparatus is shown schematically in FIG. 1 and designated by the reference numeral 11. The data from the first data processing apparatus 11 is encoded in a transmitter 13 which can be a double sideband suppressed quadrature carrier amplitude modulated transmitter. This data is then sent to first data access equipment 15 which interfaces with a plurality of telephone lines, including the line 17. In a preferred embodiment, the telephone line 17 is terminated through second data access equipment 19 by a receiver 21 which can be a double sideband suppressed carrier quadrature amplitude modulated receiver. In the receiver 21, the incoming signal is demodulated and decoded before it is forwarded to a second data processing apparatus 23. In this manner, the data from the first data processing apparatus 11 can be transmitted over the telephone line 17 to the second data processing apparatus 23.
The transmitter 13 is shown in greater detail in FIG. 2 between the first data processing apparatus 11 and the transmission data access equipment 15. An encoder 25 is connected to the data processing apparatus 11 and adapted to receive straight binary digititized data therefrom at a particular rate such as 2400 bps or 4800 bps. Within the encoder 25, incoming data is randomized, differentially encoded, and separated into an in-phase channel and a quadrature channel, which have been so designated for a reason which will be subsequently apparent. These channels will herinafter be referred to as the I channel and the Q channel respectively.
At the output of the encoder 25, the signals in the I and Q channels respectively, can include digital words or symbols dI.sub.j and dQ.sub.j, respectively, where the sub j implies the jth data symbol in a continuous series of the symbols, dI, dQ. Each of the data symbols dI.sub.j and dQ.sub.j expresses one of a plurality of data levels, the number of which depends on the speed of the operation. For example, if data is being transmitted at a rate of 2400 bps, the digital symbols will typically express data levels of .+-. 1. For 4800 bps operation, the symbols will typically express one of four levels such as .+-. 3 and .+-. 1. In the latter case, the digital symbols will each contain 2 binary bits to express one of the four levels. The digital symbols will typically occur at the rate of 1200 per second so that the modem throughput is 1200 symbols per second per channel, times b 2 bits per symbol, times 2 channels or 4800 bps.