Receivers for pulses of different widths
AssigneeNippon Steel Corporation
InventorTetuya Sugai
Life of this patent
Estimating the term…
Abstract
A data transmission system for transmitting data and subsidiary information by means of pulses of different widths corresponding to a multiple of a signal propagation time delay of a NAND gate. The system makes it possible to simplify the construction of the data transmission device to a considerable degree and at the same time to transmit data at a high speed, and includes a variety of circuits for generation and demodulation of the pulses.
Claims10
A width-modulated pulse demodulator system for receiving pulses of different widths and decoding them, said demodulator system comprising a plurality of delay elements each having a different delay time, each of said delay elements receiving said pulses of different widths, a front-edge-waveform detector circuit serially connected to the output of the delay element having the longest delay time, a plurality of rear-edge-waveform detector circuits each serially coupled to a respective one of the remaining delay elements, and a plurality of AND gates each having two inputs, one input of each AND gate being commonly connected to the output of said front-edge-waveform detector circuit, and the other input of each AND gate connected to a respective output of said rear-edge-waveform detector circuits.
A width-modulated system for receiving pulses of different widths and decoding them, said demodulation system comprising a plurality of delay elements and a corresponding plurality of rear-edge-waveform detector circuits alternately connected in series circuit arrangement with said delay elements, said circuit arrangement commencing with a rear-edge-waveform detector circuit which receives said pulses of different widths, and said circuit arrangement terminating with a delay element, a front-edge-waveform detector circuit serially coupled to said terminating delay element, and a corresponding plurality of AND gates each having two inputs, one input of each AND gate being commonly connected to the output of said front-edge-waveform detector circuit, and the other input of each AND gate connected to a respective output of said rear-edge-waveform detector circuits.
Dependencies are inferred from the claim text.