US 4,061,908 A · Method of and device for testing a digital memory

Abstract

The invention provides a compact test sequence for testing integrated memories. First, all storage positions are filled with the bit "0". Subsequently, in a given order of the addresses, the "0" bit written for each address is read; immmediately thereafter a "1" bit is written in those bit positions. The positions are again tested by reading the "1" bits. When the last address of the predetermined order is reached, the "1" is read in the same order for each address. Subsequently a "0" is written, which is finally tested by reading again. When the last address is reached, all addresses are read in the reverse order, and a "1" is written, which is tested again. When the first address is reached, all addresses are read, filled with a "0" and tested. This process may be repeated as many times as there are bits in the address. The significance of the address bits are modified to form the predetermined order, for example, by cyclic rotation. For example, in the first cycle the order may be the normal order of successive addresses, while in the second cycle first all "even" and then all "odd" addresses are treated.

Claims11

Dependent claims

A method of testing memories, in which a predetermined first number of discrete, random addressable, storage positions for binary information is provided with each storage position having a specific address, said first number being at least substantially equal to 2.sup.N and the addresses containing N binary information elements of successive significance in accordance with a first order, comprising the steps of

filling the storage positions first with a first information,
subsequently reading the storage positions during a first cycle in accordance with a first address sequence for the purpose of testing in that the address is each time changed by one unit,
subsequently filling the addressed storage positions with changed information with respect to the read-out,
reading the storage positions again for the purpose of testing in accordance with the reverse of the first address sequence, and
filling again said storage positions with changed information with respect to the latter read-out,
repeating said first cycle during a second cycle, the storage positions being assigned a different sequence in that the order of significance of the said N binary information element is modified.

3 more elements

Dependencies are inferred from the claim text.

Method of and device for testing a digital memory

Life of this patent

Method of and device for testing a digital memory

Life of this patent

Abstract

Claims11