Digital coordinator with smooth transition for offset changes

In a digital coordinator for creating a background cycle defined by a series of control pulses repeatedly cycled between a first number, N.sub.1, and a second number, N.sub.2, with the time space between the N.sub.1 control pulse and the N.sub.2 control pulse being a background cycle length, said coordinator comprising a primary pulse counter means incremented by input counting pulses for creating one in a series of said control pulses in response to a selected number of input counting pulses, said input counting pulses having a frequency for determining the cycle speed of progression of said control counts in successive count positions between the N.sub.1 control pulse and the N.sub.2 control pulse of a given background cycle, and shifting means for shifting said N.sub.1 control pulse with respect to time to correspond in time with a signalization offset signal, the improvement comprising:

• said shifting means including a counting circuit for counting count pulses created by and corresponding to said input counting pulses during a given background cycle and from a selected count position in said given cycle;
• a response means for creating a control logic signal in response to a signalization offset signal occurring before a given count position in said given cycle;
• first means responsive to said control logic signal for creating a stop signal;
• second means responsive to said control logic signal for storing the number of count pulses counted by said counting circuit prior to said offset signal;
• means responsive to said stop signal for preventing said counting pulse from incrementing said primary counting means;
• and, means for holding said stop signal for a time controlled by said number of count pulses.