Digital traffic coordinator

#This invention relates to the art of traffic control devices and more particularly to a coordinator for coordinating the signalization at a given intersection in a controlled traffic system.

#The invention is particularly applicable for use in coordinating a multiphase traffic flow pattern at a given intersection which is controlled from a remote master controller and it will be described with particular reference thereto; however, it is appreciated that the invention has broader applications and may be used as a coordinator for various traffic control systems.

#As is well known, traffic control systems often employ a master controller which can control the signalization at numerous intersections within a network or pattern of related traffic flow. Generally these systems utilize a coordinator at each intersection which determines the background cycle length of the signalization and certain programmed functions for the intersection. The master controller provides control information to the coordinator which, in turn, regulates the local controller in accordance with this and other input information. These coordinators include a means for determining the cycle length for processing the total signalization at the intersection. In addition, outputs from the coordinator control certain functions at the local intersection. Generally, this type of system requires a means for providing a selected offset of one intersection with respect to other intersections. Offset allows flow in a more efficient manner along a continuous traffic flow pattern. For instance, at certain times during the day or during certain traffic conditions, it is necessary to change the offset at different intersections. To do this, a master synchronization pulse is created at the master controller. Each of the intersections then employs a selected time delay after the master pulse before its signalization cycle is initiated. As traffic conditions change, the offset is changed by the master controller to optimize traffic flow. This type of coordinated system is well known and is generally in use in traffic control systems.

#These and other objects and advantages will become apparent from the following description taken together with the accompanying drawings in which:

#FIG. 1 is a schematic logic diagram illustrating the preferred embodiment of the present invention;

#FIG. 2 is a partial wiring and logic diagram illustrating an output module used in the preferred embodiment;

#Referring now to the drawings wherein the showings are for the purpose of illustrating a preferred embodiment of the invention only, and not for the purpose of limiting same, FIG. 1 shows a coordinator A used to control a traffic signal S at a traffic intersection TI. This schematically illustrated intersection includes a number of separate traffic phases which vary according to the configuration of the intersection and are shown only for the purposes of illustrating a representative type of intersection to be controlled by the coordinator A. A master control unit M remotely located with respect to the intersection includes certain output lines which can direct a master synchronization pulse, offset select signal and other pulses to the various coordinators located at the intersection. A variety of traffic system configurations can employ a coordinator constructed in accordance with the present invention. In the preferred embodiment, coordinator A includes a driving circuit B, a programmed output circuit or module C and an offset control circuit D which receives the master synchronize pulse MS from master controller M.

#Referring now to FIG. 1, a main cycle length pulse counter 10 is provided with two stages. The first stage counts between 0-9, as units, and the second stage counts between 0-9 as tens. These two counters are connected in decade so that counter 10 counts between 0 and 99 as pulses are received at input 12. Counter 10 can roll over to all zeros after 99 and continue the cycle length counting for a new cycle. However, in the preferred embodiment when 99 has been reached, counter 10 is inhibited until again started for the next cycle. Thus, counter 10 produces one hundred output pulses for each background cycle, which divide the background cycle into 100 equal parts or percentages. Thus, the 100 increments are designated as cycle length percentages. In the illustrated embodiment the group of leads a is designated tens and the group of leads b is designated units to produce the 0 to 99 output. Thus, the logic on leads a, b is a binary coded logic which changes at each one percent increment during the background cycle. Of course, other increments could be used for dividing the output of counter 10. For instance, the increment could be 1/2%, 1/4%, 2%, etc. This would change the required driving frequency. Counter 10 is enabled by two lines 20, 22 which are controlled by a dual stage unit such as flip-flop 30. This provides an arrangement for stopping the counter 10 at the end of its counting function when the output reaches the binary coded designation for the number 99. This flip-flop can be considered as a shifting unit for shifting counter 10 back into the 0 position for the next successive cycle timing function. Flip-flop 30 includes a D terminal connected to a positive power supply thus presenting a logic 1 at this terminal. The Q line 32 is connected to enable lines 20, 22 so that when a logic O appears in line 32, the two counter banks in counter 10 are enabled. A clock line 34 for flip-flop 30 receives a pulse when the output of counter 10 reaches the number 99. This can be provided by various arrangements. In the illustrated embodiment, an AND gate 40 has inputs 42, 44 connected to the 9 line of both counter sections to produce clocking logic when counter 10 reaches 99. This gates the logic 1 from terminal D to terminal Q of flip-flop 30. The reset line 50 for flip-flop 30 is controlled by an OR gate 52 which either receives an offset key or pulse in input 54 to reset the flip-flop or a logic on line 56 which prevents the clocking pulse from stopping counter 10. The logic on line 56 is controlled by a manual switch or switches on coordinator A, which indicate that the coordinator is in free or manual operation. Under normal circumstances, the logic 0 appears in line 56 and the coordinator A is controlled by the offset control circuit D.

#As pulses P appear at input 12, counter 10 counts between 0 and 99. At the 99 coded logic in lines a, b, flip-flop 30 is clocked to block further operation of counter 10. This resets the counter to 0% awaiting a pulse in line 32 created by gate 52 upon receipt of an offset key in lline 54. When an offset key is created by the offset control circuit D, flip-flop 30 is reset and counter 10 commences to count the next cycle for signalization by the program module C.