Arrangement for controlling thyristor networks

The method of establishing a communication path from the first to the last of a plurality of serially connected thyristors comprising a first and second main conduction electrode and a gate electrode, wherein the second main conduction electrode of each thyristor, except the last thyristor, is connected to the first main conduction electrode of a subsequent thyristor, comprising the steps of:

• A. applying a marking voltage to the first main conduction electrode of said first thyristor;
• B. producing gate currents equal to or greater than the holding current of said
• thyristors in each thyristor, in sequence and overlapped in time, from the first to the last of said thyristors;
• and
• C. producing a hold current in the second main conduction electrode of said last thyristor.

The method of establishing a communication path from the first to the last of a plurality of serially connected thyristors each comprising a first and a second main conduction electrode and a gate electrode, wherein the second main conduction electrode of each thyristor, except the last thyristor, is connected to the first main conduction electrode of a subsequent thyristor, comprising the steps of:

• A. applying a marking voltage to the first main conduction electrode of said first thyristor;
• B. producing gate currents, equal to or greater than the holding current of said thyristors, in each thyristor in sequence and overlapped in time from the first to the last of said thyristors;
• C. inhibiting the gate current produced in a given thyristor, except said last thyristor, a predetermined period of time after the production of a gate current in a subsequent thyristor;
• D. producing a hold current in the second main conduction electrode of said last thyristor;
• and
• E. inhibiting the gate current produced in said last thyristor a predetermined period of time after the production of a hold current in its second main conduction electrode.

In combination:

• a plurality of thyristors comprising a first and a last thyristor wherein the anode of each thyristor, except said last thyristor, is connected to the cathode of a subsequent thyristor;
• marking means for applying a low potential to the cathode of said first thyristor;
• a gate current generator for applying gate currents, equal to or greater than the holding current of said thyristors,to the gates of each of said thyristors in sequence and overlapped in time, from said first to said last thyristor;
• and
• holding means for applying a current, equal to or greater than the holding current of said thyristors, to the anode of said last thyristor.

The method of establishing a communication path through a plurality of serially connected thyristors comprising a first and last thyristor, and wherein the anode of each thyristor, except the last thyristor, is connected to the cathode of a subsequent thyristor, comprising the steps of:

• A. applying a low voltage to the cathode of said first thyristor;
• B. applying gate currents equal to or greater than the holding current of said thyristors to each thyristor in sequence and overlapped in time from the first to the last of said thyristors;
• and
• C. applying a hold current to the anode of said last thyristor.

The method of establishing a communication path through a plurality of serially connected thyristors comprising a first and a last thyristor, and wherein the anode of each thyristor, except the last thyristor, is connected to the cathode of a subsequent thyristor, comprising the steps of:

• A. applying a low voltage to the cathode of said first thyristor;
• B. appyling gate currents equal to or greater than the holding current of said thyristors to each thyristor in sequence and overlapped in time from the first to the last of said thyristors;
• C. inhibiting the gate current applied to a given thyristor, except said last thyristor, a predetermined period of time after the application of a gate current to a subsequent thyristor;
• D. applying a hold current to the anode of said last thyristor;
• and
• E. inhibiting the gate current applied to said last thyristor a predetermined period of time after the application of a hold current to its anode.

In combination:

• a plurality of thyristors comprising a first and a last thyristor wherein the anode of each thyristor, except said last thyristor, is connected to the cathode of a subsequent thyristor;
• timing means for generating a plurality of timing signals defining time intervals;
• marking means responsive to a first one of said timing signals for applying a low potential to the cathode of said first thyristor;
• a gate current generator responsive to said timing signals for appylying gate currents, equal to or greater than the holding current of said thyristors, to the gates of said thyristors in sequence from said first to said last thyristor;
• means responsive to said timing signals for inhibiting said gate current applied to the gate of any given thyristor, except said last thyristor, a predetermined period of time after a current equal to or greater than said holding current is applied to the gate of a subsequent thyristor;
• holding means, responsive to said timing signals, for applying a current equal to or greater than said holding current to the anode of said last thyristor;
• and
• means responsive to said timing signals, for inhibiting the gate current applied to said last thyristor a predetermined period of time after the application of a hold current to its anode.

In combination:

• a plurality of switching stages including a first stage and a last stage, said switching stages comprising n input terminals, m output terminals and n .times. m thyristors each having its cathode connected to one of said input terminals and its anode connected to one of said output terminals;
• interconnecting means for sequentially interconnecting said switching stages such that the output terminals of each switching stage, except said last switching stage, are connected to the input terminals of a subsequent switching stage;
• n marking voltage sources each uniquely associated with one of said input terminals of said first switching stage for selectively applying a low voltage to its associated input terminal;
• means for applying gate currents to selected thyristors in each of said switching stages in sequence and overlapped in time;
• means for inhibiting a gate current applied to the gate of any given thyristor after a current, equal to or greater than said holding current, flows from the anode to the cathode of said given thyristor;
• and
• m holding current sources each being uniquely associated with one of said ouput terminals of said last switching stage for selectively applying a hold current to its associated output terminal.

In combination:

• a plurality of thyristors comprising a first and a last thyristor wherein the cathode of each thyristor, except said last thyristor, is connected to the anode of a subsequent thyristor;
• marking means for applying an increased potential to the anode of said first thyristor;
• a gate current generator for drawing a gate current, equal to or greater than the holding current of said thyristors, from the gate of each of said thyrsitors in sequence and overlapped in time, from said first to said last thyristor;
• and
• holding means for drawing a current, equal to or greater than the holding current of said thyristors, from the cathode of said last thyristor.