Semiconductor memory device
AssigneeFujitsu Limited
InventorsRyoiku Togei, Akira Takei, Yoshihiko Hika, Kunihiko Wada
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Abstract
A semiconductor memory device provided with one transferring electrode, one gate electrode and one diode of a charge coupled device is produced by a process with a reduced number of steps of diffusion and patterning. Both electrodes consists of doped polycrystalline silicon and both are electrically connected to a resistive layer which consists of non-doped polycrystalline silicon. A potential barrier between the region of both electrodes is removed due to the resistive layer. Resistive layer is formed by utilization of a two-stage deposition of the polycrystalline silicon layer with appropriate mashing steps.
Claims8
A semiconductor memory device for reading and writing data in response to selected input signals, comprising in combination:
- a semiconductor material substrate having a first conductivity and including, adjacent to a given surface thereof, a doped region of a second conductivity opposite to said first conductivity, and further including a gate region adjacent to said doped region, and a memory cell region adjacent to said gate region and remote from said doped region;
- memory cell electrode means disposed above said given surface and above said memory cell region, and responsive to said selected input signals for respectively assuming one of a plurality of potentials;
- gate electrode means disposed above said given surface and above said gate region, and responsive to said selected input signals for respectively assuming one of said plurality of potentials;
- and
- insulation means between said memory cell and gate electrode means, and said substrate, for electrically shielding the latter from the former;
- said gate electrode means including, immediately adjacent to said memory cell electrode means, a resistive means for establishing a linear potential transition from the potential of said gate electrode means to that of said memory cell electrode means;
- whereby, in response to said selected input signals, electrical charge is selectably transferred to and from said doped region, respectively, from and to said memory cell region, in a speedy manner.
Dependencies are inferred from the claim text.