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AssigneeHoneywell Information Systems Inc.
InventorsPaul S. Feldman, Robert B. Johnson, Chester M. Nibby, Jr.
Estimating the term…
Apparatus and a method for generating timing signals to be utilized in latched type memories only when the address signals are valid. A CAS signal is generated in response to an RAS signal via a device which tracks the worst case delay of memory address signals and does not permit the application of the CAS signal to memory until the worst case delay of the memory address signals has been accounted for. A memory array is comprised of any combination of latched or non-latched tri-state memories. The latched memories are coupled to a data bus utilizing conventional TTL circuits in combination with a power driver to simulate conventional tri-state buffer circuits. When the power driver/drivers remove(s) power from TTL circuits, the tri-state characteristics are simulated; whereas when the power driver applies power to the TTL circuits, they operate in their normal mode and present a normal impedance between the data bus and data-out lines of the memory array.
In a computer system having a power supply, a system clock, a data bus, a main memory of the latched type having first enabling means and responsive to said first enabling means wherein data out is latched to the data bus and remains latched to said data bus for a full memory cycle of said main memory, said main memory also having second enabling means for presenting a high impedance to said data bus when no electric signal is applied to said second enabling means from said power supply, an interface apparatus for generating an electronic pulse for causing the data out to be unlatched from said data bus prior to the end of the memory cycle, said interface apparatus comprising:
The apparatus as recited in claim 4 including sixth means coupled to said address decoding means and to said third means for applying the decoded address signals to said main memory.
The data processing system having a power supply, a system clock, a data bus, a main memory of the latched type, having first enabling means and responsive to said first enabling means wherein data out is latched to the data bus and remains latched to said data bus for a full memory cycle of said main memory, said main memory also having second enabling means for presenting a high impedance to said data bus when no electronic signal is applied to said second enabling means from said power supply, and interface apparatus for generating an electronic pulse for causing the data out to be unlatched from said data bus prior to the end of the memory cycle, said interface apparatus comprising the steps of:
Dependencies are inferred from the claim text.