Sensing amplifier for capacitive MISFET memory

A sensing amplifier sensing an output signal from a capacitive MISFET memory cell containing a memory capacitance, comprising:

• an input terminal for receiving the output signal from said memory cell;
• an output terminal;
• first and second sensing MISFETs, the sources of said frist and second sensing MISFETs being connected to a first reference potential, the drain of said first sensing MISFET being connected to the gate of said second sensing MISFET and to said output terminal, the drain of said second sensing MISFET being connected to said input terminal;
• capacitive means having its one end connected to said first reference potential and the other end connected to said input terminal;
• precharge means, connected between a second reference potential and said input terminal, for precharging said capacitive means in response to a first clock signal prior to the application of the output signal from said memory cell to said sensing amplifier to preset said sensing amplifier;
• means, connected between said second reference potential and the drain of said first sensing MISFET, for coupling said second reference potential to the drain of said first sensing MISFET in response to a second clock signal after the presetting of said sensing amplifier;
• and
• a signal level shifting circuit for shifting the level of out output signal from said memory to apply the level-shifted output signal to the gate of said first sensing MISFET, said signal level shifting circuit including a drive MISFET whose gate is connected to said input terminal and a first load MISFET whose gate is connected to the drain of said first sensing MISFET, the drain of said drive MISFET being connected to said second reference potential, the source of said drive MISFET and the drain of said first load MISFET being connected to each other and to the gate of said first sensing MISFET, the gate of said first load MISFET being connected to the drain of said first sensing MISFET and the gate of said second sensing MISFET, the source of said first load MISFET being connected to said first reference potential.

A sensing amplifier for sensing an output signal from a capacitive MISFET memory cell containing a memory capacitance, comprising:

• an input terminal for receiving the output signal from said memory cell;
• an output terminal;
• a latch circut including a first and second MISFETs whose junction point is connected to said input terminal and a second inverter having third and fourth MISFETs whose junction point is connected to said output terminal, first and second clock signals being applied to the gates of said first and third MISFETs respectively, the gate of said second MISFET being connected to said output terminal;
• and
• a signal level shifting circuit connected to said input terminal at an input side thereof and to the gate of said fourth MISFET at an output side thereof for shifting the level of the output signal of said memory cell to apply the level-shifted output signal to the gate of said fourth MISFET.