Charge coupled device shift registers having an improved regenerative charge detector

A data storage system comprising a plurality of charge coupled device shift register data stores, each shift register including a plurality of stages, each including a plurality of transfer electrodes, means for applying multiphase clock signals to said electrodes to shift data signals along said shift register, data output means for said shift register adjacent a selected transfer electrode of one of said stages, said selected transfer electrode connected for application of a predetermined phase clock signal thereto;

• and regenerative charge detector means comprising in combination:
• first and second non-clocked inverter stages connected between respective voltage supply lines, means cross coupling input nodes and output nodes of said inverter stages, one of said cross coupling means including gating means connected for operation by said predetermined phase clock signal;
• said output means of said shift register connected to the input node of said first inverter stage;
• feedback means connected between the input and output nodes of said first inverter stage for precharging said nodes of said first inverter stage to a reference voltage set by a value V.sub.out = V.sub.in on an output voltage (V.sub.out) versus input voltage (V.sub.in) transfer characteristic of said inverter stages;
• and means for applying subsequent to said precharge step, said predetermined phase signal to said selected transfer electrode and said gating means, to transfer a data signal to the output means of said shift register for causing regenerative imbalance between the voltages at the output nodes of said first and second inverter stages in a sense corresponding to the level of said transferred data signal compared with that of said reference voltage;
• and logic output means coupled to the input node of said second inverter and to the output node of said second inverter for generating a logic output signal according to the sense of said imbalance;
• and means for coupling the logic means of each data store in sequence to a common system output to multiplex said logic output signals from said plurality of detector means.