Priority network for devices coupled by a common bus

A data processing system comprising a common bus having one end defined as a low priority end;

• a processor connected to the said one end of said common bus;
• a memory unit connected to said common bus;
• a plurality of peripheral devices coupled to said common bus, with the priority of said devices being determined by their proximity to said one end;
• means at each peripheral device for producing a first flag signal when a processor interrupt is requested and a second flag signal when a memory interrupt is requested;
• a plurality of peripheral device control units each associated with a peripheral device for receiving a produced flag signal and for passing an enabling signal from the highest priority control unit to the first peripheral control unit receiving a flag signal and for preventing the passage of the enabling signal to all peripheral control units having a lower priority than the first peripheral device producing a flag signal, each peripheral control unit also comprising logic means responsive to the first and the second flag signals for providing signals to said processor and said memory unit respectively, indicating an access request;
• means responsive to an access granted signal from said memory unit or said processor unit for granting access to the highest priority peripheral device requesting bus access;
• and
• bus control means for controlling times at which bus access can be granted after being requested by said control units.