Digital multi-line companded delta modulator
AssigneeInternational Business Machines Corporation
InventorGardner Dulany Jones, Jr.
Life of this patent
Estimating the term…
Abstract
A companded digital delta modulator which can encode both voice and voice band modem signals over a wide range of input levels is shown. The companding method or algorithm is based on measuring bit stream correlation and can be scaled to give substantially maximum performance over a wide range of signal types. The algorithm has a low sensitivity to digital channel errors, thus making it suitable for signal coding for satellite channels and the like. In addition, the digital design permits common hardware to simultaneously serve a large number of lines, thus permitting the substantial savings in the hardware cost per line. A further aspect of the invention concerns the ability to handle multiple bit delta modulation as well as single bit delta bit modulation in the above environment.
Claims10
A delta modulator comprising:
- a first means for comparing the amplitudes of an analog input signal and an analog feedback signal and periodically providing a first or a second output signal voltage d.sub.i as a function of said comparison;
- second means for forming the product of the output signal d.sub.i of the current period and the output signal of the next prior period d.sub.i-1 ;
- third means for summing the said product during each period with a digital reference signal;
- a first digital recursive filter means responsive to the output of said third means for generating a gain control signal .DELTA..sub.m ;
- fourth means responsive to the output from said first means and said first filter means output for generating a digital signal which is a function of the said gain control signal;
- a second digital recursive filter responsive to the said fourth means for providing a digital feedback signal;
- and
- a digital to analog converter responsive to the said second filter output for providing the said analog feedback signal.
A delta modulator for concurrently modulating in a time division manner a plurality of analog signals each appearing on one of a plurality of different lines and comprising:
- a plurality of first means, one for each said line, for comparing the amplitute of the analog signal on the line and an analog feedback signal from a common source and each periodically providing a first or a second output signal voltage d.sub.i as a function of said comparison;
- switching means for connecting said first means in a repetitive time sequence to an ouput channel;
- a memory including at least one segment of addressable storage for each line for storing parameters including the state of the output signal d.sub.i-1 for the last processing period for the line, a feedback signal S.sub.m-1 and a gain control signal .DELTA..sub.m-1 both calculated from the two next prior states of the output signal d;
- of addresses corresponding to the number of lines being serviced and with each said address a plurality of control clock pulses the first of which access the stored past history for the line being serviced;
- means for applying said address signals to the said switch and memory means;
- means for converting the accessed feedback signal S.sub.m-1 to an analog signal as the said common source signal applied to the said plurality of first means;
- processing means under control of the said plurality of control clock pulses for calculating new values for S.sub.m-1, .DELTA..sub.m-1 and d.sub.i-1 based on a predetermined algorithm, the current output d.sub.i and the prior values of S.sub.m-1, .DELTA..sub.m-1 and d.sub.i-1 ;
- and
- means responsive to the last of said plurality of control clock pulses for storing the said calculated values in the memory at the then indicated address.
A multi-bit delta modulator comprising:
- first means for comparing the amplitudes of an analog input signal and an analog feedback signal and periodically providing a first or a second output signal voltage d.sub.i as a function of said comparison, oscillator means operating at said periodic rate for sampling the said first means to effect the periodic comparison and for driving a counter means said counter means including as many stages as the multi-bit modulation;
- gate means responsive to the first output from said counter for connecting the output d.sub.i to a second means once per cycle of operation of said counter means;
- said second means responsive to the output of the said gate means for forming the product of the output signal d.sub.i provided by the gate means and the output signal of the next prior period of operation d.sub.i-1 ;
- third means for summing the said product during each period with a digital reference signal;
- a first digital recursive filter means responsive to the output of said third means for generating a gain control signal;
- shift register means responsive to the gain control signal from the first digital recursive filter for shifting the output therefrom by a predetermined amount;
- dividing means responsive to the output of said shift register means and to the counter output for providing a unity output during the first output from said counter and a different fraction thereof during the remaining counts of said repetitive counter output;
- fourth means responsive to the output from said dividing means and the said first means for generating in each period of counter operation n digital signals which are a decreasing function of the said gain control signal;
- a second digital recursive filter responsive to the output from said fourth means for providing n sequential digital feedback signals per cycle of counter operation;
- and
- a digital to analog converter responsive to the said second digital filter output providing the said analog feedback signal.
Dependencies are inferred from the claim text.