US 4,058,777 AGranted

Oscillating circuit

AssigneeHochiki Corporation

InventorsKatsutoshi Kuwabara, Katsuaki Goto

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Abstract

An oscillator circuit comprised of three bistable circuits connected in cascade, a circuit for generating first timing signals, and a circuit for generating second timing signals. Output signals from the series of bistable circuits are applied to enable the circuits for generating timing signals, and the timing signals are applied to an input of the series of bistable circuits to change the states of the bistable circuits. After a first time interval has elapsed the first timing signal changes the state of a first bistable circuit which in turn successively changes the states of the other bistable circuits. After a second time interval has elapsed after the changes of state effectuated by the first timing signal, the second timing signal changes the state of the first bistable circuit which in turn successively changes the states of the other bistable circuits, so that the bistable circuits repetitively change state with a period equal to the sum of the first and the second time intervals.

Claims8

Dependent claims

An oscillator circuit, comprising:

first, second and third bistable circuits each having a pair of stable operating states and each having a respective input port for receiving input signals and a respective output port for developing output signals thereat, said bistable circuits being responsive to input signals applied to their respective input ports for operating in states determined by said input signals and for developing respective output signals having values according to the states said bistable circuits are operating in;
connecting means connecting said bistable circuits is cascade in the named order so that a change of state of said first bistable circuit will effectuate successive changes of state of said second and said third bistable circuit, whereby the output signal of said third bistable circuit is representative of the state of said first bistable circuit;
first timing means connected to the output port of said third bistable circuit to recieve the output signals developed thereat for developing a first timing signal effective to change the state of said first bistable circuit from a first state to a second state thereof after a first time interval has elapsed after said third bistable circuit has changed from a state corresponding to the second state of said first bistable circuit to a state corresponding to the first state of said first bistable circuit and for applying said first timing signal to the input port of said first bistable circuit;
and
second timing means connected to the output port of said third bistable circuit to receive the output signals developed thereat for developing a second timing signal effective to change the state of said first bistable circuit from the second state to the first state thereof after a second time interval has elapsed after said third bistable circuit has changed from a state corresponding to the first state of said first bistable circuit to a state corresponding to the second state of said first bistable circuit and for applying said second timing signal to the input port of said first bistable circuit, whereby the states of said bistable circuits oscillate between their respective stable operating states with a period equal to the sum of said first time interval and second time interval.

2 more elements

An oscillator circuit comprising:

three pairs of complementary field effect transistors each comprising a first field effect transistor having a channel of a first conductivity type and a second field effect transistor having a channel of a second conductivity type, wherein the first and second transistor of each pair of complementary field effect transistors have their respective gates connected together to define a gate node for the pair and have their respective drains connected together to define an output node for the pair, and wherein said three complementary transistor pairs are connected in cascade with the output node of a first pair connected to the gate node of a second pair and with the output node of the second pair connected to the gate node of a third pair;
a power supply line connected to the source of each first transistor of said three complementary transistor pairs having the first channel conductivity type;
an earth line connected to the source of each second transistor of said three complementary transistor pairs having a second channel conductivity type;
and
a charging and discharging loop comprising a capacitor connected between the gate node of the first transistor pair and said earth line for developing a potential to bias the gates of the first pair of transistors, a first resistor connected between the output node of the third transistor pair and said capacitor to define a charging path to charge said capacitor when the first transistor of the third complementary pair is conductive, a series combination of a second resistor and a diode connected between the output node of the third pair and second capacitor and with said diode having a polarity to define a discharge said capacitor through the second transistor of the third complementary pair;
wherein said capacitor is charged through the first transistor of the third pair until it is sufficiently charged to switch the respective conductive states of said first transistor pair and whereby successively switch the respective conductive states of said second and third transistor pairs to discharge said capacitor until the respective conductive states of said first pair are again switched, whereby the switching of the conductive states of the respective transistor pairs is repetitive.

3 more elements

Dependencies are inferred from the claim text.