Surface charge signal processing apparatus

Signal correlator apparatus comprising

• a substrate of semiconductor material having a major surface,
• first means forming a first plurality of charge storage regions adjacent said major surface of said substrate,
• second means forming a second plurality of charge storage regions adjacent said major surface of said substrate, each forming with a respective first charge storage region a respective charge storage cell,
• said first means including a first plurality of electrodes, each electrode insulatingly overlying a respective charge storage region of said first plurality, said electrodes being interconnected,
• said second means including a second plurality of electrodes, each insulatingly overlying a respective charge storage region of said second plurality,
• a plurality of intermediate charge storage regions adjacent said major surface of said substrate, each separating first and second storage regions of a respective charge storage cell,
• a plurality of first gating electrodes each insulatingly overlying a respective one of said intermediate regions, said gating electrodes being interconnected,
• each first storage electrode forming with said substrate a first capacitance, each second storage electrode forming with said substrate a second capacitance, each first gating electrode forming with said substrate a third capacitance, the sum of said first capacitance and said third capacitance being equal to said second capacitance,
• means for introducing into each of successive ones of said cells a respective one of successive quantities of charge, each quantity being proportional to a respective sample of a time varying analog signal, each quantity of charge including first and second portions of equal value, each first portion of a quantity of charge being solely contained in the first storage region of a respective cell and each second portion of said quantity of charge being contained in the second storage region of said respective cell,
• means for applying to each of said second storage electrodes a voltage waveform selected from a first voltage waveform and a second voltage waveform of the same periodicity in response to a respective one of a series of successive binary bits of a reference word,
• a. the bits of a first value in said series of bits forming a first group of bits and providing said first voltage waveform to the second electrodes associated with a first group of cells, said first voltage waveform enabling said first portions of said quantities of charge to be stored in said first storage regions of said first group of cells and said second portions of said quantities of charge to be stored in the second storage regions of said first group of cells during a first interval of a period thereof, and causing said first portions of said quantities of charge to be transferred to said second storage regions of said first group of cells during a second interval of a period thereof,
• b. the bits of a second value in said series of bits forming a second group of bits and providing said second voltage waveform to the second electrodes associated with a second group of cells, said second voltage waveform enabling said first portions of said quantities of charge to be stored in said first storage regions of said second group of cells and said second portions of said quantities of charge to be stored in the second storage regions of said second group of cells during a first interval of a period thereof, and causing said second portions of said quantities of charge to be transferred to said first storage regions of said second group of cells during a second interval of a period thereof,
• means connected in circuit with said first storage electrodes for sensing the total net charge transferred to and from said first charge storage regions during said second interval.