Serial FFT processing unit
AssigneeNippon Electric Co., Ltd.
InventorKunihiko Niwa
Life of this patent
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Abstract
An FFT processing unit of simplified construction comprises one or more arithmetic stages serially connected. Each stage has a plurality of recursive arithmetic paths each consisting of a delay element, a simplified multiplier for multiplying by .+-.1 and .+-.j where j = .sqroot.-1, and an adder. The adder is supplied with a serial input digital data series and the output is provided to the delay element and multiplier connected in series. A switch successively selects the output signals obtained from the plurality of recursive arithmetic paths. A second multiplier multiplies the signals selected by the switch by predetermined coefficients.
Claims12
An FFT processing unit comprising one or more serially connected arithmetic stages, each arithmetic stage having
- a. a plurality of recursive arithmetic paths, each recursive arithmetic path consisting of
- 1. a delay element,
- 2. a simplified multiplier means fed with an output signal obtained from said delay element for multiplying said output signal by any one of .+-.1 and .+-.j where j is equal to .sqroot.-1, and
- 3. an adder means fed with a serial input digital data series and an output signal of the simplified multiplier means at its first and second input terminals, respectively, and feeding its output signal to an input terminal of the delay element,
- said recursive arithmetic paths being connected in parallel so that said serial input digital data series are given at their respective input terminals;
- b. a switch means for successively selecting output signals obtained from said plurality of recursive arithmetic paths;
- and
- c. a second multiplier means for multiplying input signals given through said switch means by predetermined coefficients.
An FFT processing unit comprising one or more serially connected arithmetic stages, each arithmetic stage having
- a. a plurality of recursive arithmetic paths, each recursive arithmetic path consisting of
- 1. a simplified multiplier means for multiplying by any one of .+-.1 and .+-.j where j is equal to .sqroot.-1,
- 2. a delay element for delaying an output signal obtained from the simplified multiplier means, and
- 3. an adder means fed with a serial input digital data series and an output signal of the delay element at its first and second input terminals, respectively, and feeding its output signal to an input terminal of the simplified multiplier means,
- said recursive arithmetic paths being connected in parallel so that said serial input digital data series are given at their respective input terminals;
- b. a switch means for successively selecting output signals obtained from said plurality of recursive arithmetic paths, and
- c. a second multiplier means for multiplying input signals given through the switch means by predetermined coefficients.
Dependencies are inferred from the claim text.