Asynchronous dual function multiprocessor machine control

An apparatus for controlling a machine having input devices for generating input signals representing the actual electrical states of the input devices in response to the machine operation and further having output devices for receiving output signals commanding the electrical state of the output devices to modify the machine operation, the apparatus comprising:

• a. a single data bit contact bus;
• b. means connected to the contact bus and the devices on the machine for interfacing the input and output signals between the contact bus and the input and output devices respectively;
• c. a single data bit logic processor means connected to the contact bus and including
• 1. means for storing logic instructions representing a pattern of predetermined states of the input signals thereby defining a desired cycle of operation of the machine, and
• 2. means responsive to the storing means and connected to the contact bus for producing the output signals in response to the actual states of the devices on the machine corresponding to the predetermined states of said devices;
• d. a data processor means connected to the contact bus and operating asynchronously with the logic processor means, said data processor means including
• 1. means responsive to one of the output signals for selecting a stored program of arithmetic instructions,
• 2. data storage for storing data signals, and
• 3. means responsive to the selecting means and the data signals for executing the arithmetic instructions to cause a further input signal to be available on the contact bus for use by said logic processor means;
• and
• e. data communication means connected to the data processor means for transferring the data signals to and from the data processor means.

An apparatus for controlling a machine having input devices for generating single bit input signals representing the actual electrical states of the input devices in response to the machine operation, output devices for receiving single bit output signals commanding the electrical state of the output devices to modify the machine operation, and other devices for generating multiple bit data signals, the apparatus comprising:

• a. a single data bit contact bus;
• b. means connected to the contact bus and the input and output devices for interfacing the input and output signals therebetween;
• c. a single data bit logic processor means connected to the contact bus and including
• 1. means for storing logic instructions representing a pattern of predetermined states of the input and output devices thereby defining a desired cycle of operation of the machine, and
• 2. means responsive to the storing means and connected to the contact bus for producing the output signals in response to the actual states of the devices on the machine corresponding to the predetermined states of said devices;
• d. a multiple bit data bus;
• e. means connected to the data bus and the other devices for interfacing the data signals therebetween;
• f. a plurality of multiple bit data processor means connected to the contact bus and the data bus and operating asynchronously with the logic processor means, each of the data processor means including
• 1. means connected to the data bus and the data processor means for transferring the data signals threbetween,
• 2. means responsive to one of the output signals for selecting a stored program of arithmetic instructions, and
• 3. means responsive to the selecting means and the data signals for executing the arithmetic instructions to cause a further input signal to be available on the contact bus for use by said logic processor means.

An apparatus for controlling the operation of a machine, said machine having input devices for generating single bit input signals representing the actual electrical states of the input devices and output devices for operating the machine in response to single bit output signals commanding the electrical states of the input devices, the apparatus comprising:

• a. a single data bit contact bus;
• b. means connected to the contact bus and the input and output devices for interfacing the input and output signals therebetween;
• c. a single data bit logic processor means connected to the contact bus and including
• 1. a memory for storing a series of memory words representing the desired states and device addresses of the input and output devices and logic instructions associated therewith, thereby simulating the desired cycle of operation of the machine,
• 2. means for continuously reading the memory words in an iterative fixed sequential cycle to provide the device addresses on the contact bus, and
• 3. means connected between the memory and the contact bus for generating the output signals in response to the actual operating conditions on the machine as represented by the input signals corresponding to the desired operating conditions on the machine as represented by the memory words;
• d. a data processor means connected to the contact bus and operating asynchronously with the logic processor means, said data processor means including
• 1. a program store for storing a number of macroinstruction programs each containing a series of arithmetic instructions,
• 2. means connected between the contact bus and the program store for selecting one of the programs in response to one of the output signals,
• 3. means responsive to the program store for decoding each macroinstruction ot produce a number of microinstructions and timing signals,
• 4. a data store for storing a number of data signals, and
• 5. means connected to the data store and the decoding means for executing the microinstructions to generate a control signal to the selecting means thereby causing the data processor means to transmit a further input signal to the contact bus in response to a device address corresponding to the further input signal;
• and
• e. data communication means connected to the data processor for transferring the data signals to and from the data communication means.

An apparatus for controlling a machine having input devices for generating input signals representing the actual electrical states of the input devices in response to the operation of the machine, output devices for receiving output signals commanding the actual electrical states of the output devices to control the operation of the machine, and other devices for generating and receiving data signals, the apparatus comprising:

• a. a single data bit contact bus;
• b. an interface circuit connected between the contact bus and the input and output devices for controlling the communication of the input and output signals between the contact bus and said input and output devices;
• c. a logic processor including
• 1. a logic program storage circuit containing memory words defining a predetermined pattern of desired conditions of the input and output devices and associated device addresses, and
• 2. means responsive to the logic program storage circuit and the contact bus for producing the output signals in response to the actual conditions on the machine as represented by the input signals corresponding to the desired conditions as represented by the memory words;
• d. a data bus;
• e. a data interface circuit connected between the data bus and the other devices for controlling the communication of data signals between the data bus and the other devices;
• f. a data processor operating asynchronously with said logic processor and including
• 1. a multiplexing circuit connected between the data bus and the data processor for multiplexing the data signals between the data bus and the data processor,
• 2. a data store responsive to the multiplexing circuit for storing data signals,
• 3. a macroinstruction program store responsive to the contact bus for providing a set of arithmetic instructions in response to one of the output signals and a corresponding device address;
• and
• 4. an arithmetic unit responsive to the data store, the multiplexing circuit and the program store for executing the set of arithmetic instructions using the data signals to cause a further input signal to be provided on the contact bus in response to corresponding device address.