US 4,058,682 AGranted

Expandable memory for PCM signal transmission

AssigneeSocieta Italiana Telecomunicazioni Siemens S.p.A.

InventorsRoberto Delle Donne, Luigi Musumeci

Life of this patent

Estimating the term…

Loading patent…

Abstract

An incoming bit stream of a first bit frequency, divided into a succession of n-bit words, is converted into an outgoing bit stream of a second bit frequency with the aid of two n-stage buffer registers alternately loaded by two sets of interleaved writing pulses, on every n.sup.th cycle of the first bit frequency, with incoming words which are alternately read out on every n.sup.th cycle of the second bit frequency by two sets of interleaved reading pulses. A logic network detects the coincidence of a reading pulse from one set with either of two guard pulses immediately preceding and succeeding, respectively, each writing pulse of the corresponding set; upon such coincidence, a switching network transposes the two sets of writing pulses to restore an original relative pulse position in which the reading pulses of each set occur substantially midway between writing pulses of the same set.

Claims7

Dependent claims

An expandable memory for converting an incoming bit stream of a first bit frequency, divided into a succession of n-bit words where n is an integer greater than 2, into an outgoing bit stream of a second bit frequency, comprising:

first timing means controlled by the incoming bit stream for generating on a first pair of outputs a pair of interleaved pulse trains of a cadence 1/2n times said first bit frequency;
second timing means independent of said incoming bit stream for generating on a second pair of outputs a second pair of interleaved pulse trains of a cadence 1/2n times said second bit frequency, the pulses of each train of said second pair being normally spaced from the pulses of corresponding trains of said first pair;
bit-storing means including a pair of n-stage buffer registers, with writing inputs respectively connected to said first pair of outputs and with reading inputs respectively connected to said second pair of outputs;
first circuit means for alternately writing the words of said incoming bit stream into said buffer registers under the control of said first pair of pulse trains;
second circuit means for alternately reading the words written in said buffer registers under the control of said second pair of pulse trains;
monitoring means connected to said first and second circuit means for detecting a near-coincidence of a pulse from one of said second pair of pulse trains with a pulse from the corresponding one of said first pair of pulse trains;
and
switchover means controlled by said monitoring means for transposing the pulse trains on one of said pairs of outputs, thereby re-establishing a normal spacing between the pulses of corresponding trains of said first and second pairs of pulse trains.

5 more elements

Dependencies are inferred from the claim text.