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US 4,057,848 AGranted
Address translation system
AssigneeHitachi, Ltd.
InventorKenji Hayashi
Life of this patent
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Abstract
In an electronic computer employing virtual storage system, the mapping of plural logical spaces -- logical addressing capability -- onto larger real space is made possible so that a conventional program can be applied to a computer system furnished with a main memory having a great capacity.
Claims7
An address translation system for mapping a plurality of logical spaces onto a real space, comprising
- a logical address register in which a logical address is set;
- a table lookaside buffer for storing translation pairs each including said logical address and a corresponding real address to translate said logical address set in said logical address register into said real address whose bit number is larger than that of said logical address;
- a searching means for judging whether said table lookaside buffer contains the same logical address as that set in said logical address register or not;
- an output means for outputting the real address of the translation pair corresponding to said logical address when said logical address is contained in said table lookaside buffer;
- and
- a real address register in which the real address from said output means is set.
3 more elements
An address translation system for mapping a plurality of logical spaces onto a real space, comprising
- a logical address register in which a logical address including an upper portion to specify a desired region and a lower address portion to represent a relative position in said region, is set;
- a table lookaside buffer to store translation pairs, each including said upper address portion of said logical address and the upper address portion of a real address which corresponds to said upper address portion of said logical address and whose bit number is larger than that of said upper address portion of said logical address;
- a searching means for judging whether said table lookaside buffer contains the same upper address portion as said upper address portion in said logical addres register or not;
- an output means for outputting the upper address portion of the real address of the translation pair corresponding to said upper address portion of said logical address when said upper address portion of said logical address is contained in said table lookaside buffer;
- and
- a real address register in which said upper address portion of said real address from said output means and the lower address portion from said logical address register are set.
3 more elements
An address translation system for mapping a plurality of logical spaces onto a real space, comprising
- a logical address register in which a logical address is set;
- a table lookaside buffer having a plurality of memory locations, each storing at least one translation pair including a first portion having at least one arbitrary bit of said logical address, and a real address corresponding to said logical address, the number of bits of said real address being greater than that of said logical address;
- an addressing means for reading a desired translation pair out of the memory location of said table lookaside buffer, specified by a second portion which is the content of said logical address register other than said first portion;
- comparison means for comparing the first portion of the logical address read out of said table lookaside buffer with the first portion from said logical address register;
- a real address register;
- and
- an output means for outputting to said real address register a real address corresponding to the address for comparison means outputs a coincidence signal.
4 more elements
An address translation system for mapping a plurality of logical spaces onto a real space, comprising
- a logical address register in which a logical address consisting of an upper address portion to specify a desired region and a lower address portion to represent a relative position in said region, is set;
- a table lookaside buffer having a plurality of memory locations, each storing at least one translation pair including a first portion having at least one arbitrary bit of the upper address portion of said logical address and, an upper address portion of a real address corresponding to said upper address portion of said logical address, the number of bits of said real address being greater than that of said logical address;
- an addressing means for reading a desired translation pair out of the memory location of said table lookaside buffer, specified by a second portion which is the content of said upper portion of said logical address register other than said first portion;
- comparison means for comparing the first portion of the logical address read out of said table lookaside buffer with the first portion from said logical address register;
- an output means for outputting the upper address portion of the real address corresponding to the address for which the comparison means outputs a coincidence signal;
- and
- a real address register in which the upper address portion of the real address from said output means and the lower address portion from said logical address register, are set.
4 more elements
Dependencies are inferred from the claim text.