Bus steering structure for low cost pipelined processor system

In a word processing system including a CPU, a memory, and a plurality of I/O devices which operate at speeds slower than said CPU and said memory, apparatus for controlling the flow of information among said CPU, said memory, and said I/O devices comprising:

• a first unidirectional buss connected to the output of the CPU for transmitting information signals from the CPU;
• a second unidirectional buss connected to the output of said memory for transmitting information signals from said memory;
• a third unidirectional buss connected to the input of said CPU for transmitting information signals to said CPU;
• a bidirectional buss connected to said I/O devices for transmitting information to and from said I/O devices;
• decoding means connected to said CPU for decoding control signals from the CPU;
• and
• gating means responsive to said decoding means and connected to said first unidirectional buss, said second unidirectional buss, said third unidirectional buss, and said bidirectional buss for receiving information from said first and second unidirectional busses and said bidirectional buss and transferring the received information onto said third unidirectional buss or said bidirectional buss.