P+ Silicon integrated circuit interconnection lines
AssigneeRCA Corporation
InventorMurray Henderson Woods
Life of this patent
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Abstract
An improved interconnecting line for an integrated circuit comprising a P+ silicon island having an optional first layer of silicon dioxide or a like material thereon and a second layer of silicon nitride or a like material adjacent the first layer, is provided. The line may be manufactured by improvements in the standard P channel MOS or MNOS processing method wherein the line is formed concomitantly with the island upon definition of the silicon. The line may be subsequently coated with silicon dioxide during formation of a gate oxide for a MNOS device and then coated with silicon nitride.
Claims14
In combination with a plurality of heteroepitaxial silicon mesa devices on a common substrate, at least one of said mesa devices comprising a first doped region and a second differently doped region, an improvement comprising:
- a means for interconnecting one of said regions of said at least one mesa device to another of said mesa devices, said means comprising a P+ silicon region having a first insulating coating thereon and a second insulating coating means for preventing oxidation of said P+ silicon region, said second insulating coating being located adjacent said first insulating coating.
In combination with a plurality of silicon semiconductor mesa devices on a common substrate at least one of said mesa devices comprising a source region and a drain region separated by a channel region, an improvement comprising:
- a means for interconnecting one of said regions of said at least one device to another of said devices, said means comprising a P+ silicon region having a first insulating coating thereon and a second insulating coating for preventing oxidation of the P+ silicon region, said second insulating coating being located adjacent the first insulating coating.
A process for making a P+ doped low resistance interconnection between a plurality of heteroepitaxial silicon integrated circuit elements formed on an insulating substrate comprising the steps of:
- a. forming a P+ doped interconnecting strip between said elements;
- b. coating the strip with an insulating coating;
- and
- c. coating the insulating coating with means for preventing substantial out-diffusion of P impurities from the silicon strip.
Dependencies are inferred from the claim text.