Analog-to-digital encoder
AssigneeAssociation pour le Developpement de l'Enseignement et de la Recherche en Systematique Appliquee (A.D.E.R.S.A.)
InventorClaude Timsit
Life of this patent
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Abstract
This encoder comprises a series of resistors for determining the reference voltages, and comparators having at least one pair of outputs A and B. First inputs of said comparators are connected respectively to said resistors and second inputs of said comparators are connected to the voltage to be encoded through an impedance adaptor stage. The outputs A and B of the pairs of outputs of each comparator are respectively connected to the outputs B and A of the following comparator and constitute first and second output groups. The first and second groups are connected respectively to the inputs of a comparator constituting a bit of smallest weight of the encoder and the outputs A and B of the other pairs of outputs are connected in a similar manner to comparators constituting bits of greatest weight.
Claims11
A high-speed analogue-to-digital encoder for converting an input analogue signal into a combination of N bits, the encoder comprising:
- a first group of comparators each having a test input and a reference input;
- a source of reference voltages feeding a resistive network having a plurality of series connected resistors, and connected in parallel to said reference inputs;
- an input circuit for feeding an analogue voltage to be encoded in parallel to said test inputs;
- at least a pair of current outputs from each said comparators of said first group for delivering a logic current signal resulting from the comparison achieved in the comparator and a logic current complementary signal for generating lower order bits;
- additional pairs of current outputs from some comparators of said first group of comparators, for generating higher order bits;
- a second group of comparators, each having a first and a second current inputs, and at least a current output;
- said inputs of said comparators of said second group being connected to said outputs of said comparators of said first group in such a manner that each comparator of said second group delivers a bit of a predetermined order of the voltage to be encoded.
Dependencies are inferred from the claim text.