Read only memory

A solid state read only memory unit comprising,

• a plurality of bit locations arranged as a matrix of rows and columns of field effect transistor (FET) devices wherein a first logic level is indicated when a gate connection is present and a second logic level is indicated when a gate connection is absent and wherein each FET device includes first and second electrodes connected to the source and drain thereof and a gate which may enable transistor action when a gate connection is present;
• first addressing means for imparting a charge to the first electrodes of a selected row of said FET devices;
• second addressing means for imparting a charge to the gate connectors of a selected column of said FET devices;
• sensing means connected to said second output electroes of said selected row and including circuit means for precluding flow of direct current at said second output electrodes whereby the logic level of the bit location at the intersection of said selected row and said selected column is determined by the presence or absence of a charge transferred between said first electrode and said second electrode resulting from the presence or absence of a gate connector at such bit location.

A solid state read only memory unit comprising a plurality of bit locations arranged in rows and columns with each bit location having first and second output electrodes and a gate position, said bit location being capable of transistor action between said first and second electrodes when a gate is installed at said gate position, said bit location upon being addressed by placing the first output electrode at a first potential and applying a potential to make said gate position active indicating a first logic level at said second output electrode when a gate is installed at said gate position and a second logic level at said second output electrode when a gate is not installed at said gate position;

• first address means including a series of source lines each connected to the first output electrodes of a row of said bit locations, a plurality of first address circuits and first decoding means for selecting at least one source line in accordance with the input received from said first address circuits;
• second address means including a series of gate connecting lines each connected to gates installed in a column of bit locations, a plurality of second address circuits and a second decoding means interconnected with said second address circuits and said gate connecting lines for selecting one of said gate connecting lines in accordance with the input received from said second address circuits;
• sense means including a plurality of sense lines each connected to a row of bit location second output electrodes;
• and
• switch means selectively operable to connect all sense lines to a common potential.

A solid state read only memory unit comprising,

• a plurality of bit locations arranged as a matrix of rows and columns of field effect transistor (FET) devices wherein a first logic level is indicated when a gate connection is present and a second logic level is indicated when a gate connection is absent and wherein each FET device includes first and second electrodes connected to the source and drain thereof and a gate which may enable transistor action when a gate connection is present;
• first addressing means for connecting said first electrodes of a selected row of said FET devices to a means for inducing a potential difference between said first and second electrodes;
• second addressing means for imparting a charge to the gate connectors of a selected column of said FET devices;
• sensing means connected to said second output electrodes of said selected row and including circuit means for precluding flow of direct current at said second output electrodes whereby the logic level of the bit location at the intersection of said selected row and said selected column is determined by the presence or absence of a charge transferred between said first electrode and said second electrode resulting from the presence or absence of a gate connector at such bit location.