Logic circuit for bistable D-dynamic flip-flops

A logic circuit for a dynamic D-flip-flop assembled with complementary field effect transistors having insulated grids comprising:

• a power of supply having a positive pole, a negative pole, and at least three logic gates (A', B', C'), each of which produces an internal variable (A, B, C), wherein each gate is formed by at least three field effect transistors with insulated grids connected in series between the positive pole and ground, and wherein each gate is controlled by at least two variables, one being an input clock signal (H), the first gate (A') including a first transistor (T.sub.1) with a first type of conductivity having a source electrode connected by a first node (N.sub.1) to the positive pole, and a drain electrode connected by a second node (N.sub.2) to the source electrode of a second transistor (T.sub.2) with the same type of conductivity, the drain electrode of said second transistor (T.sub.2) is connected by a third node (N.sub.3) on the one hand to the drain electrode of a third transistor (T.sub.3) with a second type of conductivity whose source electrode is connected by a fourth node (N.sub.4) to ground, and on the other hand to the grid of two transistors (T.sub.4, T.sub.6) of a second gate (B'), the grids of said first and third transistors (T.sub.1, T.sub.3) of the first gate (A') are connected to the input of an external command variable (D), and the gird of said second transistor (T.sub.2) of said first gate (A') is connected to said input of the clock signal (H), the second gate (B') of the circuit includes a fourth transistor (T.sub.4) having the first type of conductivity, and a grid connected to the drain electrode of said second transistor (T.sub.2) of the first gate (A'), its source electrode being connected by a fifth node (N.sub.5) to the positive pole and its drain electrode by a sixth node (N.sub.6) to the source of a fifth transistor (T.sub.5) having the first type of conductivity, the drain electrode of which is connected by a seventh node (N.sub.7) on the one hand to the drain electrode of a sixth transistor (T.sub.6) having a second type of conductivity, whose grid is connected to the drain electrode of said third transistor (T.sub.3) of the first gate (A'), on the other hand the seventh node (N.sub.7) connects the drain electrode of the fifth transistor (T.sub.5) to the grids of two transistors (T.sub.8, T.sub.9) of the third gate (C'), the source electrodes of said sixth transistor (T.sub.6) is connected by an eighth node (N.sub.8) to the drain electrode of a seventh transistor (T.sub.7) with the second type of conductivity, whose source electrode is connected by a ninth node (N.sub.9) to ground, the grids of said fifth and seventh transistors (T.sub.5, T.sub.7) are connected to said input of the clock signal (H);
• the third gate (C') of the structure includes an eighth transistor (T.sub.8) of the first type of conductivity, whose grid is connected to the drain electrode of said sixth transistor (T.sub.6) of the second gate (B'), its source electrode is connected by a tenth node (N.sub.10) to the positive pole and the drain electrode by an eleventh node (N.sub.11) on the one hand to the output (C = Q) of the circuit, and on the other hand to the drain electrode of a ninth transistor (T.sub.9) with the second type of conductivity, whose grid is connected to the drain electrode of said sixth transistor (T.sub.6) of the second gate (B'), its source electrode being connected by a twelfth node (N.sub.12) to the drain electrode of a tenth transistor (T.sub.10) with the second type of conductivity, whose source electrode is connected by a thirteenth node (N.sub.13) to ground, and the grid to said input of the clock signal (H).