US 4,056,851 AGranted

Elastic buffer for serial data

AssigneeRCA Corporation

InventorsNorman Hovagimyan, John Michael Link

Life of this patent

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Abstract

An elastic buffer, including a single random access memory, receives information bits at a rate determined by a receiving clock, and transmits the information bits at a rate determined by an output clock, where the clocks are not exactly synchronous. A read-write memory timing circuit synchronized by the output clock repeatedly produces a read pulse followed by first and a second spaced write pulses. In response to the read pulse, a bit is read out from the memory at an address determined by the contents of an address counter. In response to the first write pulse, a first received bit, if received, is written into the memory at an address determined by the contents of a read address counter. In response to the second write pulse, a second received bit, if received, is written into the memory at an address determined by the contents of the read address counter. An alarm is given if the numbers in the address counters are equal, indicating that the memory is empty, or filled and about to overflow.

Claims6

Dependent claims

An elastic buffer for receiving information bits at a rate determined by a receiving clock, and transmitting the information bits at a rate determined by an output clock, where the clocks are not exactly synchronous, comprising

a two-bit data input buffer,
a random access memory,
a read-write memory timing circuit synchronized by said output clock and repeatedly producing a read pulse followed by first and a second spaced write pulses,
a read address counter and a write address counter,
means responsive to said read pulse to read out a bit from said memory at an address determined by the contents of said read address counter, and then increment said counter,
means responsive to said first write pulse and the presence of a first received bit in said two-bit buffer to write said bit into said memory at an address determined by the contents of said write address counter, and then increment said counter, and
means responsive to said second write pulse and the presence of a second received bit in said two-bit buffer to write said bit into said memory at an address determined by the contents of said write address counter, and then increment said counter.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 05/724,915Filed 20 Sep 1976
Granted: 1 Nov 1977
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 5/14
Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations: for…
H04J 3/0626
Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers: plesiochronous multiplexing systems, e.g.…
H04L 25/05
Details ; arrangements for supplying electrical power along data transmission lines: electric or magnetic storage of signals before transmitting…
G06F
Computing and data processing