Memory control system using plural buffer address arrays
AssigneeHitachi, Ltd.
InventorChikahiko Izumi
Life of this patent
Estimating the term…
Abstract
In a data processing system in which a single main memory is shared by two or more basic processing units, each unit is provided with a first buffer address array which stores the addresses of data stored in the associated buffer memory and is searched by this processing unit and with second buffer address arrays which store the copy of the content of the first buffer address array and are searched by the store addresses from the other processing units, so that the information stored in the buffer memory of one processing unit may be prevented from becoming different from the information stored in the main memory when another processing unit performs a storing operation, without degrading the processing efficiency of the system.
Claims7
In a memory control system for a data processing system, which memory control system includes a main memory, a basic processing unit which carries out processing operations with respect to information read-out from and written into said main memory, at least one additional processing unit which also carries out processing operations with respect to information read-out from and written into said main memory, said main memory being adapted to be accessed by said processing units, the improvement wherein at least said basic processing unit comprises
- a buffer memory for reading-out and writing-in a predetermined amount of information stored in said main memory;
- first register means, coupled to said main memory, for storing the address of said main memory which corresponds to information stored in said buffer memory;
- first detector means, coupled to said first register means, for detecting whether or not there is stored in said first register means an address corresponding to an address signal produced within said basic processing unit representative of an address location in said main memory;
- second register means, coupled to said main memory, for storing a copy of the contents of said first register means;
- second detector means, coupled to said second register means, for detecting the storage address in said main memory into which storage address information is to be written by an additional processing unit;
- and
- means, coupled to said first and second detector means, and responsive to the writing of information into said storage address of said main memory by said additional processing unit, so that information stored in said buffer memory may differ from that stored in said main memory and may, therefore, no longer be valid information, for invalidating a predetermined amount of information which is contained within the information stored in said buffer memory, said predetermined amount of information including that information which is written into said main memory by said additional processing unit.
In a memory control system for a data processing system, which memory control system includes a main memory, a basic processing unit which carries out processing operations with respect to information read-out from and written into said main memory, a plurality of additional processing units which also carry out processing operations with respect to information read-out from and written into said main memory, said main memory being adapted to be accessed by said processing units, the improvement wherein at least said basic processing unit comprises
- a buffer memory for reading-out and writing-in a predetermined amount of information stored in said main memory;
- first register means, coupled to said main memory, for storing the address in said main memory which corresponds to information stored in said buffer memory;
- first detector means, coupled to said first register means, for detecting whether or not there is stored in said first register means an address corresponding to an address signal produced within said basic processing unit representative of an address location of said main memory;
- a plurality of second register means, respectively corresponding to the plurality of additional processing units, and coupled to said main memory, for storing a copy of the contents of said first register means;
- a plurality of second detector means, respectively corresponding to the plurality of additional processing units, and respectively coupled to said plurality of second register means, for detecting the fact that the respective addresses of information to be written into said main memory by different ones of said plurality of additional processing units are stored in corresponding ones of said plurality of second register means;
- and
- means, responsive to the result of detection by said second detector means, representative of the fact that information stored in said buffer memory may differ from that stored in said main memory and, therefore, may no longer be valid information, for invalidating a predetermined amount of information stored in said buffer memory, said predetermined amount of information including that information which is written into said main memory by any one of said plurality of additional processing units.
Dependencies are inferred from the claim text.