FET device with reduced gate overlap capacitance of source/drain and method of manufacture

A metal gate field effect transistor having reduced parasitic capacitance comprising

• a. a semiconductor substrate of a first conductivity type,
• b. a first insulating layer including at least two openings disposed on the substrate,
• c. at least two diffused regions of a second conductivity type disposed in the substrate and beneath the openings in the layer,
• d. a insulating layer disposed on the first insulating layer and in the opening, the second layer in the opening having a thickness greater than the combined thickness of the second layer outside the opening and the first insulating layer,
• e. a third insulating layer disposed on the substrate and between the diffused regions but not extending over the diffused regions,
• f. a control electrode disposed on the third layer and at least a portion of the second layer, the parasitic capacitance of the gate overlap of the second layer being substantially reduced by the increased thickness of the second layer relative to the third insulating layer, and
• g. terminals connected to the diffused regions.

A semiconductor device having reduced parasitic capacitance comprising

• a. a semiconductor substrate of a first conductivity type,
• b. at least one diffused region of a second conductivity type including an outdiffused portion disposed in the substrate,
• c. a first insulating layer disposed on the substrate and surrounding a portion of the diffused region,
• d. a second insulating layer over the diffused region having a thickness greater than the first layer, a third thin insulating layer disposed on the substrate and extending over the outdiffused region but not the diffused region, and
• e. a conductor disposed on the second and third insulator layers and overlying the outdiffused region and at least a portion of the diffused region whereby the parasitic capacitance due to the conductor overlap of the diffused region is less than the parasitic capacitance due to the conductor overlap of the outdiffused region.

A metal gate FET device having reduced gate overlap capacitance of source and drain comprising

• a. a semiconductor substrate of a first conductivity type,
• b. at least two spaced diffused regions of a second conductivity type disposed in the substrate as source and drain, a first insulating layer disposed on the substrate and surrounding the spaced diffused regions, each diffused region including an outdiffused portion,
• c. a second insulating layer disposed on the diffused regions,
• d. a third insulating layer disposed on the substrate between the diffused regions and extending over the outdiffused portion but not the diffused regions, and
• f. a conductor disposed on the third insulating layer extending over at least a portion of the second insulating layer whereby the gate to source and drain overlap capacitance is substantially less than 0.039 picofarads per mil along one side of the gate dimensions over the diffused region.