Electronically alterable diode logic circuit
AssigneeBell Telephone Laboratories, Incorporated
InventorKarvel Kuhn Thornber
Life of this patent
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Abstract
A crosspoint (X-Y) matrix array of electrically reprogrammable memory logic elements, such as an array of dual dielectric insulated gate field effect transistor (IGFET) structures, is interconnected in a single electrically reprogrammable diode logic array circuit, both for computing the logic function(s) of many variables and for writing and erasing the function(s). Each logic element's high current path is in series with a separate unidirectional diode in order to prevent sneak paths. Electrical access circuitry is also provided for computing the logic function(s) of many variables, each funtion being electrically alterable.
Claims27
A logic circuit which comprises
- a. a row column array, MxN in number, of three-terminal electrically unidirectional and reprogrammable logic cells, each cell having a first and a second high current carrying terminal and a third low current carrying gate terminal,
- b. a plurality of M first electrically conductive row line means for connecting together the third terminals of all cells in each row to a different gate write-in row terminal,
- c. a plurality of M second electrically conductive row line means for connecting together the first terminals of all cells in each row to a different row line signal terminal,
- d. a plurality of N third electrically conductive column line means for connecting together the second terminals of all cells in each column to a different one of said column lines, each column line connected at one terminal thereof to a different two-terminal column electrical load element for inhibiting current in the opposite sense of direction from said unidirectional cell and each column line having a column signal terminal.
Semiconductor apparatus which comprises
- a. a row-column MxN array of three-terminal logic cells, each cell having a different first high current cell terminal and a different second high current cell terminal thereby defining a separate high current path for each cell, each cell consisting essentially of a different electrically programmable semiconductor memory element in series with a separate unidirectional inhibitor element for passing high current through the logic cell between the first and second high current cell terminals only in one sense of direction and inhibiting current in the other sense of direction, each said memory element having a low current cell gate terminal for the application of voltage to program the memory element,
- b. a first plurality, M in number, of electrically conductive row gate line means, each for mutually connecting together the said low current gate terminals of the memory elements in all cells of each row to a different gate write-in row terminal,
- c. a second plurality, M in number, of electrically conductive row line means, each for mutually connecting together the first high current terminals of all cells in each row to a different row line signal terminal,
- d. a third plurality, N in number, of electrically conductive column line means for mutually connecting together the second high current terminals of all cells in each row to a different column line signal terminal and to a column load terminal, and
- e. means for connecting each column load terminal to a first terminal of a different two-terminal column load element for inhibiting current in said one sense of direction.
Dependencies are inferred from the claim text.