Differential input-differential output transistor switching cell

A differential input, differential output current cell comprising,

• a. a pair of matched level shifting input transistors arranged symmetrically in opposite left and right branches and each level shifting transistor having,
• 1. a common electrode joined at a first node, said first node connected to a first bias circuit means for supplying switch current,
• 2. a control electrode and
• 3. an output electrode for handling switch current in each respective circuit branch supplied from a source, one of said control electrodes receiving a digital input signal, the other of said control electrodes receiving a threshold adjustment voltage from a connected second bias circuit means, said digital input signal having at least two discrete states including a low state for turning on one of said level shifting transistors and the other transistor off and a high state for turning off the one transistor and turning on the other transistor, said second bias circuit means for generating a constant voltage threshold at a low impedence, said constant voltage threshold having a voltage between said low state and said high state,
• b. a pair of matched output transistors each respective transistor symmetrically connected in said opposite left and right branches, each output transistor having,
• 1. a common electrode joined at a second node, said second node connected to receive steering current from one of said output transistors,
• 2. a control electrode connected to a respective output electrode of a level shifting input transistor for receiving switch current therefrom and initiating transfer of steering current from one circuit branch to another in response to a change in switch current between branches,
• 3. an output electrode connected to a respective load for communicating steering current therewith,
• c. a pair of matched voltage dropping means arranged symmetrically in said opposite left and right branches, one end of said voltage dropping means connected to a respective control electrode of an output transistor, the other end mutually connected to a third bias circuit means,
• d. a third bias circuit means connected to said voltage dropping means for compensating transients in transfering current between left and right circuit branches whereby a logic input signal specifies one of said circuit branches wherein switch current switches steering current from one output electrode of said output transistors to the other.