Memory module with means for generating a control signal that inhibits a subsequent overlapped memory cycle during a reading operation portion of a reading memory cycle

A random access memory module for connection over a bus to a digital data processing system that, for each of successive memory cycles including reading and writing memory cycles, initiates a data transfer by transmitting binary address signals and asynchronous control signals that include a starting control signal for initiating a data transfer with said memory module and a binary direction control signal for controlling the direction of the data transfer between said random access memory module and the digital data processing system, said random access memory module comprising:

• A. addressable storage means for storing digital data in addressable storage locations therein,
• B. address decoding means for producing an enabling signal when said address decoding means receives, from the digital data processing system, binary address signals that identify a said storage location in said addressable storage means, and
• C. control means connected to said addressable storage means and said address decoding means, said control means including:
• i. memory cycle control means responsive to the enabling signal and the starting control signal for producing a selected one of the reading and writing memory cycles, each said memory cycle including a reading operation during which digital data is retrieved from an identified one of said locations in said addressable storage means and a succeeding writing operation during which data is stored in said identified location in said addressable storage means,
• ii. timing signal means for generating a timing signal that corresponds to the interval of a reading operation during the operation of said memory cycle control means,
• iii. reading signal means for generating a reading signal in response to a state of the direction control signal that designates a transfer of digital data from said memory module to the digital data processing system, and
• iv. means responsive to said timing signal means and to said reading signal means for transmitting to the digital data processing system a BUS OCCUPIED signal that is coterminous with the timing signal during a reading cycle, the BUS OCCUPIED signal inhibiting the initiation of any succesive memory cycles by the digital data processing system until the completion of a reading operation during a reading memory cycle and the termination of the BUS OCCUPIED signal.